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Gererate netlist with Verilog-A

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georgemailo

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Hello everyone.

I want to take one cell (with a schematic view) from my library and place it N times in a row in series. For example that could be a N-bit adder which is composed by 1bit cells. Can I do that in verilog-a using a for loop or something similar? Is there any other way?

I repeat that the original cell has only a schematic view (and a symbol). It does NOT have a verilog-a model.

Thank you all.
 

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