I have an entity for clock_gating in my design, which should be synthesized as a specific clock gating cell in one of the libraries that I have loaded into Genus.
However, Genus doesn't seem to recognize this cell to be used, and instead synthesizes my clock gating entity to separate cells (latches, NAND and INV), which causes some issues downstream.
One way to do a quick fix is to change the generated netlist manually, but that feels like a hack and I want to find a more generic solution for this issue.
Is there a way to map an entity to a specific cell from my libraries in Genus?
Thanks in advance!