Apr 12, 2004 #1 G gedou Newbie level 6 Joined Apr 10, 2002 Messages 11 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 72 we know that VHDL provides a generic mechanism for writing parameterized models.But,can we do the same in verilog?if yes,how?
we know that VHDL provides a generic mechanism for writing parameterized models.But,can we do the same in verilog?if yes,how?
Apr 12, 2004 #3 J jimjim2k Advanced Member level 3 Joined May 17, 2001 Messages 996 Helped 23 Reputation 46 Reaction score 13 Trophy points 1,298 Activity points 7,178 Hi The "parametrized modules" invocation could help you. Search the net for a rich set of docs. If you could not find valuable examples, I will write for you myself. tnx
Hi The "parametrized modules" invocation could help you. Search the net for a rich set of docs. If you could not find valuable examples, I will write for you myself. tnx