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"generic mechanism" in verilog?

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gedou

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we know that VHDL provides a generic mechanism for writing parameterized models.But,can we do the same in verilog?if yes,how?
 

Hi

The "parametrized modules" invocation could help you.

Search the net for a rich set of docs.
If you could not find valuable examples, I will write for you myself.



tnx
 

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