Generic Mapping of 19-bits over an 8-bit

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theres no problem. You can use attributes:

signal lfsrPart1 : std_logic_vector(g_seed1'range);

This way lfsrPart1 will always have the same size as the generic. You can actually create ports without a size and so the ports get sized when they are instantiated, giving the design an implied generic if you like.
 
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    FvM

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