xtcx
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Hi friends, I need a clarity in generic mapping in VHDL. I have a situation where the top file writes 19-bits into the entity named RND where the generic delcaration in entity is only 8-bits
This RNDcomponent file is instantiated two times in a Top file, as like this
Now the actual RND file has generic declaration like this
This code was given to us by stating it was a working code compiled sometime back with ISE7.0 version in 2005. Now we are to re-design this. Now I'm getting error "stating generic size mismatch error while mapping g_tap1 of 19-bits in mod2:RND for 8-bits.
My doubt :
What happens if we pass slv of 19-bit width at the top file generic map into the sub component which has only 8-bit delcaration or vice versa. Will the 19-bit value resize to 8-bit before assigning?.
Or Does the sub-component generic declared signal g_tap1 (in my eg) also adjust based on the bit-width specified in top file or what?.
Actual error : Line 235: Expression has 19 elements ; expected 8
Please clarify me. Thanks.
This RNDcomponent file is instantiated two times in a Top file, as like this
Code:
mod1 : RND
Generic map ( g_tap1 => "0000000000000000000", -- 19-bits
g_tap2 => "00000000") -- 8-bits
port map (.........) -- some mapping, so leave it
mod2 : RND
Generic map ( g_tap1 => "00", -- 2-bits
g_tap2 => "0000000000000000000") -- 19-bits
Now the actual RND file has generic declaration like this
Code:
entity RND is
Generic ( g_tap1 => "00000000", -- 8-bits
g_tap2 => "0000000000000000000"); -- 19-bits
port ( .......);
end RND;
This code was given to us by stating it was a working code compiled sometime back with ISE7.0 version in 2005. Now we are to re-design this. Now I'm getting error "stating generic size mismatch error while mapping g_tap1 of 19-bits in mod2:RND for 8-bits.
My doubt :
What happens if we pass slv of 19-bit width at the top file generic map into the sub component which has only 8-bit delcaration or vice versa. Will the 19-bit value resize to 8-bit before assigning?.
Or Does the sub-component generic declared signal g_tap1 (in my eg) also adjust based on the bit-width specified in top file or what?.
Actual error : Line 235: Expression has 19 elements ; expected 8
Please clarify me. Thanks.