Generating sine wave for testbench in systemVerilog

[drk15]

Hello All,
I am trying to generate a sine wave with frequency 5GHz with 0.4V offset and 0.4V amplitude. This is what I do.

// Testbench
`timescale 1ps/10fs
import "DPI" pure function real sin (input real rTheta);
module testbench;
// Declarations
parameter sampling_time =1;
const real pi = 3.1416;

bit sampling_clock=0;
real freq = 5e9;
real offset = 0.4;
real ampl = 0.4;
real sine_out;

initial begin

$fsdbDumpvars(0,"testbench" , "+all");
$timeformat(-12,3,"ps",1);
#1000 $finish;

end


always sampling_clock = #(sampling_time) ~sampling_clock;
always @(sampling_clock) begin
sine_out = offset + (ampl * sin(2*pi*freq*$time));
$write("Sine value at time=%0g is =%0g\n",$time,sine_out);

end
endmodule


After doing this, I check the generated waveform in nWave, but I think the generated wave is not 5G frequency but a lot more. I do not understand what is wrong.
ANy help will be appreciated.

Thanks.