Generating SAIF file

dayana42200 · Dec 3, 2018

Hello everyone.

Im wanted to generate the SAIF file from ISIM. Im using Xilinx ISE Design Suite 14.7

Ive found the method to generate SAIF file. Please also refer to the attach figure.

1. Implement the top module

2. Generate post-place and route simulation model.

3. Now change to simulation mode then change to post route and click the
generate post-place and route simulation model.

4. Click simulate post-place and route model.

However, there is an error.

WARNING:HDLCompiler:929 -
"C:/Users/User/Desktop/Design/Local/ProcessingElement/ProcessingElement/
netgen/par/ProcessingElement_timesim.v" Line 6097: Top-level design unit glbl
specified more than once, ignoring glbl of library work
ERROR:Simulator:778 - Static elaboration of top level Verilog design unit(s) in
library work failed

Please help me to solve the error or any other method to generate SAIF
file.

Thank you very much.

dpaul · Dec 3, 2018

ERROR:Simulator:778 - Static elaboration of top level Verilog design unit(s) in library work failed

Can you confirm that the design simulates successfully?

dayana42200 · Dec 4, 2018

Yup for behavioral simulation

Started : "Simulate Behavioral Model".

Determining files marked for global include in the design...
Running fuse...
Command Line: fuse -intstyle ise -incremental -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -lib secureip -o C:/Users/User/Desktop/Design/Local/ProcessingElement/ProcessingElement/ProcessingElement_tb_isim_beh.exe -prj C:/Users/User/Desktop/Design/Local/ProcessingElement/ProcessingElement/ProcessingElement_tb_beh.prj work.ProcessingElement_tb work.glbl {}
Running: D:\14.7\ISE_DS\ISE\bin\nt\unwrapped\fuse.exe -intstyle ise -incremental -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -lib secureip -o C:/Users/User/Desktop/Design/Local/ProcessingElement/ProcessingElement/ProcessingElement_tb_isim_beh.exe -prj C:/Users/User/Desktop/Design/Local/ProcessingElement/ProcessingElement/ProcessingElement_tb_beh.prj work.ProcessingElement_tb work.glbl
ISim P.20131013 (signature 0x8ef4fb42)
Number of CPUs detected in this system: 4
Turning on mult-threading, number of parallel sub-compilation jobs: 8
Determining compilation order of HDL files
Analyzing Verilog file "C:/Users/User/Desktop/Design/Local/ProcessingElement/ProcessingElement/Sync_Rst_TWO_Input_Adder.v" into library work
Analyzing Verilog file "C:/Users/User/Desktop/Design/Local/ProcessingElement/ProcessingElement/Sync_Rst_Three_Input_Adder.v" into library work
Analyzing Verilog file "C:/Users/User/Desktop/Design/Local/ProcessingElement/ProcessingElement/Sync_Rst_CompTop.v" into library work
Analyzing Verilog file "C:/Users/User/Desktop/Design/Local/ProcessingElement/ProcessingElement/Sync_Rst_CompLeft.v" into library work
Analyzing Verilog file "C:/Users/User/Desktop/Design/Local/ProcessingElement/ProcessingElement/Sync_Rst_CompDiag.v" into library work
Analyzing Verilog file "C:/Users/User/Desktop/Design/Local/ProcessingElement/ProcessingElement/Top.v" into library work
Analyzing Verilog file "C:/Users/User/Desktop/Design/Local/ProcessingElement/ProcessingElement/Left.v" into library work
Analyzing Verilog file "C:/Users/User/Desktop/Design/Local/ProcessingElement/ProcessingElement/Diagonal.v" into library work
Analyzing Verilog file "C:/Users/User/Desktop/Design/Local/ProcessingElement/ProcessingElement/CompMax.v" into library work
Analyzing Verilog file "C:/Users/User/Desktop/Design/Local/ProcessingElement/ProcessingElement/SW_Affine.v" into library work
Analyzing Verilog file "C:/Users/User/Desktop/Design/Local/ProcessingElement/ProcessingElement/LookUpTable.v" into library work
Analyzing Verilog file "C:/Users/User/Desktop/Design/Local/ProcessingElement/ProcessingElement/CompMaxSoFar.v" into library work
Analyzing Verilog file "C:/Users/User/Desktop/Design/Local/ProcessingElement/ProcessingElement/ProcessingElement.v" into library work
Analyzing Verilog file "C:/Users/User/Desktop/Design/Local/ProcessingElement/ProcessingElement/ProcessingElement_tb.v" into library work
Analyzing Verilog file "D:/14.7/ISE_DS/ISE//verilog/src/glbl.v" into library work
Starting static elaboration
Completed static elaboration
Fuse Memory Usage: 160432 KB
Fuse CPU Usage: 812 ms
Compiling module LookUpTable(ComputeDataWidth=8)
Compiling module Sync_Rst_TWO_Input_Adder(Compute...
Compiling module Sync_Rst_CompDiag(ComputeDataWid...
Compiling module Diagonal(ComputeDataWidth=8)
Compiling module Sync_Rst_Three_Input_Adder(Compu...
Compiling module Sync_Rst_CompTop(ComputeDataWidt...
Compiling module Top(ComputeDataWidth=8)
Compiling module Sync_Rst_CompLeft(ComputeDataWid...
Compiling module Left(ComputeDataWidth=8)
Compiling module CompMax(ComputeDataWidth=8)
Compiling module SW_Affine(ComputeDataWidth=8)
Compiling module CompMaxSoFar(ComputeDataWidth=8)
Compiling module ProcessingElement
Compiling module ProcessingElement_tb
Compiling module glbl
Time Resolution for simulation is 1ps.
Waiting for 8 sub-compilation(s) to finish...
Compiled 15 Verilog Units
Built simulation executable C:/Users/User/Desktop/Design/Local/ProcessingElement/ProcessingElement/ProcessingElement_tb_isim_beh.exe
Fuse Memory Usage: 166932 KB
Fuse CPU Usage: 1062 ms
Launching ISim simulation engine GUI...
"C:/Users/User/Desktop/Design/Local/ProcessingElement/ProcessingElement/ProcessingElement_tb_isim_beh.exe" -intstyle ise -gui -tclbatch isim.cmd -wdb "C:/Users/User/Desktop/Design/Local/ProcessingElement/ProcessingElement/ProcessingElement_tb_isim_beh.wdb"
ISim simulation engine GUI launched successfully

Process "Simulate Behavioral Model" completed successfully

dpaul · Dec 4, 2018

I don't using ISE or have even generated a saif, but technically you should be following this to generate the SAIF file...
https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ism_cl_saif.htm

But ERROR:Simulator:778 - Static elaboration of top level Verilog design unit(s) in library work failed indicates that some library has not been compiled properly or a something like that...

ads-ee · Dec 4, 2018

what is in the isim.cmd (batch) file?

To run a simulation with any primitives you need to have glbl called out as a separate design on the simulator command line (at least that is how it works with Vivado simulator and modelsim (haven't used isim much). glbl has a bunch of globals and drives the GSR net that is in the primitives to generate the power-on reset when a simulation starts.

It has to be loaded in parallel with your testbench, not as part of the design. e.g. for modelsim you would have vsim -L simprims tb_and_design_with_primitives glbl

Did you `include glbl or instantiate it?

dayana42200 · Dec 5, 2018

I couldnt find .cmd file inmy project directory

I do have glbl file. I am confuse which file to simulate. The testbench or glbl file? Please refer to the attachment.

- - - Updated - - -

@ads-ee

I found whats in the isim.cnd file

onerror {resume}
saif open -scope ProcessingElement_inst -allnets -file "C:/Users/User/Desktop/Design/Local/ProcessingElement/ProcessingElement/xpower_time_sim.saif";
wave add /
run 1000 ns;
saif close;

ads-ee · Dec 5, 2018

You simulate your testbench not the glbl. glbl is for globals that are necessary to simulate designs which included Xilinx unisims/simprims primitives.

e.g. here is a snippet from the unisims FDCE primitive

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
module FDCE #(
...
);
 
...
    reg [0:0] IS_D_INVERTED_REG = IS_D_INVERTED;
 
    tri0 glblGSR = glbl.GSR;
...

and in glbl GSR is initialized with the following:

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
assign (strong1, weak0) GSR = GSR_int;
    assign (strong1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;
 
    initial begin
    GSR_int = 1'b1;
    PRLD_int = 1'b1;
    #(ROC_WIDTH)
    GSR_int = 1'b0;
    PRLD_int = 1'b0;
    end

as you can see glbl is hierachically referenced as a top-level simulation file, hence my previous post about it being called out on a simulator command line along with the testbench.

dayana42200 · Dec 6, 2018

@ads-ee

Thank you for the explanation. Ive tried to simulate the testbench and it works.

Generating SAIF file

dayana42200

Junior Member level 3

Attachments

dpaul

Advanced Member level 5

dayana42200

Junior Member level 3

dpaul

Advanced Member level 5

ads-ee

Super Moderator

dayana42200

Junior Member level 3

Attachments

ads-ee

Super Moderator

dayana42200

dayana42200

Junior Member level 3

Similar threads

Code Verilog - [expand]
1 2 3 4 5 6 7 8 9	module FDCE #( ... ); ... reg [0:0] IS_D_INVERTED_REG = IS_D_INVERTED; tri0 glblGSR = glbl.GSR; ...

Generating SAIF file

Junior Member level 3

Attachments

Advanced Member level 5

Junior Member level 3

Advanced Member level 5

Super Moderator

Junior Member level 3

Attachments

Super Moderator

Junior Member level 3

Similar threads

Privacy & Transparency

Privacy & Transparency