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Generating Layout from Schematic

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pavan garate

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I know how to simulate a circuit using TSPICE and want to generate its layout. Is it possible to generate the layout from the schematic? If it is not possible, then can we generate a Verilog file from the schematic in TSPICE and then use that Verilog file to generate the layout in MICROWIND?

I’m using TSPICE version 14.11 and MICROWIND version 3.1.
 

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