Generating I2S signal: Difference between standard and left justified

[knicklicht]

Hello all,

I am trying to generate a correct I2S signal to interact with my PCM1681 DAC using my FPGA. By default it uses a left justified signal but I want to use the "standard" I2S format. The datasheet states the following:

Next you can see my current signal. The data line alternates between 0x000000 and 0xffffff every 256 left right cycles.
Overall:

Closeup:

If I set the device to use left justified I see an analog square wave that alternates between 2.5V and 5V. This is because the first bit is set to 0 as per the standard I2S definition and I2S uses two's complement:

However, when I set the device to use standard I2S I should see a signal alternating between 0V and 2.5V (omitting the offset). However, this is not the case:

I have checked the signal again and again but I cannot find my mistake. I have also checked that I set the right value using I2C in register 0x09. Does someone see the issue?

 

[KlausST]

Hi,

first:
Transmitter and receiver must match. They need to use the same format (setup)

What we see is the result of changing only one partner´s format.
Makes no sense.

****

The problem now is that in on case the MSB is decoded as SIGN, in the other case it is not decoded as SIGN.

signed: 0x000000 and 0xFFFFFF are just one LSB off. You are not able to see that tiny difference on a scope.
unsigned: 0x000000 and 0xFFFFFF are full scale off. You see full scale jump in output voltage.
(or half FS if decoded as shifted 1 bit right)

Klaus

 

[knicklicht]

Ah, yea I totally missed that. I thought that 0xFFFFFF in two's complement is -2^24/2 but it's -1 :-D . Thanks for pointing that out.