Hi,
if first rising edge is at 0 ns, the second one is at 101ns, third rising edge is at 202 ns, and so on.
from 0 to 101ns is 101ns,
from 101 to 202 is also 101 ns.
from your description i thought the folowing time should be 102ns.
Please check what you need:
A) 0 (+101) 101 (+101) 202 (+101) 303 (+101) 404...
or
B) 0 (+101) 101 (+102) 203 (+103) 306 (+104) 410 ...
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Please specify the timing of the falling edges.
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Please specify the upper limit of timing (if distance increases 101, 102, 103...)
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With an FPGA and a clock of 1GHz, a counter that counts every ns (1Ghz), a second counter for the TOP value,
and a comparator comparing both counters --> on compare match the GHz counter is reset and the TOP counter is incremented.
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Another - not time constant but frequency constant - solution is to work with NCO.
but it decrements frequency: 10.0MHz, 9.9MHz, 9.8MHz, 9.7MHz and so on
This is also possible with FPGAs. But maybe this is even more complicated.
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To relax timing, maybe you can live with 100, 100, 102, 102, 104, 104, (2ns steps)
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Maybe you can provide more information about your application.
If you need this for ADC undersampling triggering. Then there are better solutions...
Klaus