Generating a pulse of 100ns

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mehanathan

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Sir/Madam,

I am trying to generate a low going pulse of 100ns and after 100ns the pulse must be HIGH.
I am using a clock of 50MHz.

Methods i have used so far but couldnot synthesize it.
1. Using a counter to count upto 5 and after 5 the reset pin goes high. it was simulated but couldnot synthesize.
2. Using a shift register of 5 flipflops and propagating HIGH after 5 clock pulses.

Above all two programs was simulated but i couldnot synthesize in Signaltap analyzer.
In signaltap analyzer the pulse remains HIGH always...

I have attached the simulation graph too..

 

Hi,

Use a counter (3 bits at least) with clock enable and reset.
Mind the reset input must not depend on enable signal

Use a comparator (or a simple AND2, bit0 and bit2) to detect count=5
The inverted output of the comparator is used to disable the counter
And it is used for your desired 100ns output.

To get a clean output you should synchronize it with the 50MHz clock (DFF)

*******
With the reset of the counter you set the counter to zero andthe output goes low
Counting 0, 1, 2, 3, 4, will give a low output.
As soon as the counter is 5 the comparator is high and disables the counter from counting..

On power up it is a bit dangerous to generate a 100ns pulse, because VCC might not be stable and also the clock source might not be stable. If you want to simulate this: mind to initialize all FF and counters to zero at powerup.

********
Better show us your schematic or hdl files and error description instead of simulator output.

Klaus
 
Hi sir,

HDL files are shown with the different methods that i ded.

METHOD 1: 
Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
 
entity pulsein is
    port(clk:in std_logic;
         reset:out std_logic);
end entity;
 
architecture rtl of pulsein is
    signal clken:std_logic;
    signal counten:std_logic;
begin
    process(clk)
    variable count:integer range 0 to 5;
    begin
        if (count=0) then 
            reset<='0';
            counten<='1';
        end if;
        clken<=clk and counten;
        if(clken='1') then
            count:=count+1;
            if(count=5) then
                reset<='1';
                counten<='0';
            end if;
        end if;
    end process;
end rtl;


METHOD 2:

Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
entity pulsein is
    port(clk:in std_logic;
         reset:out std_logic:='0');
end entity;
 
architecture rtl of pulsein is
    signal c:std_logic_vector(5 downto 0):="000000";
    component dfflop is
    port(clk:in std_logic;
         d:in std_logic;
         output:out std_logic:='0');
    end component;
begin
    c(0)<='1';
    comp: for i in 0 to 4 generate
        comp1: dfflop port map(clk,c(i),c(i+1));
    end generate;
    reset<=c(5);
end rtl;


METHOD 3:

Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
entity pulsein is
    port(clk:in std_logic;
         reset:out std_logic:='0');
end entity;
 
architecture rtl of pulsein is
    signal c:std_logic_vector(5 downto 0):="000000";
    component dfflop is
    port(clk:in std_logic;
         d:in std_logic;
         output:out std_logic:='0');
    end component;
begin
    c(0)<='1';
    comp: for i in 0 to 4 generate
        process(clk)
        begin
            if(clk='1' and clk'event) then
                c(i+1)<=c(i);
            end if;
            reset<=c(5);
        end process;
 
    end generate;
    reset<=c(5);
end rtl;


On power up itself generating a pulse can be wrong but my dac needs to be reset on power up by applying a low going pulse on its reset pin.

Help me avoiding the bug.

Thanking you,
 
Last edited by a moderator:

Well the first method is wrong because yo havent made a clocked process. Inside the process, you must wrap all the code inside

if rising_edge(clk) then --new method since 1993

or

if clk'event and clk = '1' then --old method since 1987

I would also advise against using variables, as their behaviour may lead to unregistered logic, even inside a clocked process.


The easiest method for this may be this code:

Code VHDL - [expand]
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signal reset_dly : std_logic_vector(4 downto 0) := "00000";
 
process(clk)
begin
  if rising_edge(clk) then
    reset_dly  <= reset_dly(3 downto 0) & '1';
  end if;
end process;
 
reset <= reset_dly(4);
 
Hi,

but my dac needs to be reset on power up
Click to expand...

Im sure in the datasheet there is a MINIMUM of 100ns.

Usually:
There are uprocessor supervisory devices they generate a reset pulse on power up (some 100ms, that should be no problem for the DAC)
Wire this as common hardware reset on your PCB. and feed this common signal to all devices with reset input.


Klaus
 

mehanathan said:
Sir/Madam,

I am trying to generate a low going pulse of 100ns and after 100ns the pulse must be HIGH.
I am using a clock of 50MHz.

View attachment 110405
Click to expand...

Try The Following Code:

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity PULSE is
    Port ( CLK : in  STD_LOGIC;
           RST_PULSE : out  STD_LOGIC);
end PULSE;
 
architecture Behavioral of PULSE is
 
    signal rst1, rst2, rst3, rst4, rst5 : std_logic:='0';
 
begin
 
    process(CLK)
    begin
        if(CLK'event and CLK = '1') then
            rst1    <= '1';
            rst2    <= rst1;
            rst3    <= rst2;
            rst4    <= rst3;
            rst5    <= rst4;
        end if;
    end process;
    
    RST_PULSE   <= rst5;
 
end Behavioral;
 
Last edited by a moderator:
Statements inside if statement are concurrent so all rst_pulse becomes HIGH at once wen the clock event has occured. isn't it????
 

mehanathan said:
Statements inside if statement are concurrent so all rst_pulse becomes HIGH at once wen the clock event has occured. isn't it????
Click to expand...

Yes, and no. As they are signals, it behaves like registers. Signals assignments only schedule a signal to get updated at some point in the future. Inside a process, this assignment will take place when the process suspends. And you've assigned each signal with the old value of the other signals, hence the shift register.
 

On every CLK event the Old value of R.H.S gets assigned to L.H.S, Hence in this case on the 5th CLK U will get Logic '1' at the O/P.
 
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