Generating a desired synthesizable binary pulse train on FPGA using VHDL

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chaitanya163

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Hello everyone

I am new to VHDL programming and FPGA.
I have a virtex - 4 FPGA and I wish to generate a binary pulse train of 16 pulses from FPGA using VHDL programming. My desired pulse train will be like "1011100111000110"(min pulse width = 30 ns).
I have a clock of 100 MHz and I am able to divide the clock frequency to get the clock of 10MHz (clock frequency required for my application). Also I am aware of the fact that "Wait for" statement can not be used for synthesizing as it can only be used for test bench and simulation purposes.

So I am struggling with this problem. I am wondering if I can use "after Xns" command in my VHDL code or if there is any other way to do it.

I will be very thankful if any feedback or advice is provided. Your response will truly be appreciated. Kindly provide your valuable suggestions.

Thanking you
Regards
 

you need to start again. For a start your maths is wrong. a 10MHz clock has a period of 100ns, so you cannot create the minimum pulse width of 30ns with this clock. 100MHz has a period of 10ns, so is ideal (clock division by means of a counter, or any logic, like a toggle bit, is very bad practice in FPGAs - you should use a PLL or DCM).

Secondly, you have gone straight for the non-synthesisable constructs - wait for and after keywords. These are simulation only ideas - how do you expect a wait for N ns or after n ns would look in real hardware?

I suggest starting over - ON PAPER. Draw out the circuit to acheive the desired pulse train, and only when you have the logic DRAWN correctly, start your VHDL over again.

HDL stands for Hardware Description Language - so if you dont understand the hardware, how can you expect to describe it?

Most VHDL tutorials show you the templates needed for the various logic elements, get yourself reading one, or a good text book.
 

chaitanya163,

Tricky, has covered the "stop thinking software" pretty well, so I'll add there are three very easy ways to approach this:

1. an FSM that generates the sequence
2. a counter and a look up table
3. a shift register loaded with the sequence

Of the 3 the shift register approach is probably the simplest to implement and the counter-LUT will use the least number of resources given the length of the sequence.

Regards
 

Hi thank you for your suggestions.


So I have 16 digital IO pins on my FPGA kit , so if I wish to generate for example 10 bit pulse train then will I have to use the 10 bit shift register for the input signal ?
Also do I have to use 10 pins for the input signal and 10 pins for the output signal ? Is it possible to send an input signal (i.e. Input : in std_logc_vector(N-1 downto 0) on single pin and have the output shift register sequence on the same pin of my FPGA kit (i.e. Q : out std_logic_vector(N-1 downto 0)) ?

I apologize for asking about basic stuff but kindly help me as I am new to this topic. It will be very kind of you to provide me any advice on this. Hoping to hear from you soon.

Thanking you
Regards
 

why cant you you just do it with a clock input? the shift registers are stored internally and do not need access to the pins, unless you need to load them from an external source.
 

Hi Tricky

I am unfortunately not aware of any method of doing it with the clock. It will be very kind of you to let me know how it can be done.

Thanks
Regards
 

Have you studied any digital logic design prior to this project? Given the lack of understanding on how to do this (very simple) project I get the feeling that your digital logic design skills aren't adequate for the task. Perhaps you should review that subject first.

Regardless, this what you might want to implement...
On the FPGA kit there will be a clock oscillator that is connected to some pin on the FPGA. The documentation will have the pin to use. That clock will be used in the design to clock a shift register that you can load/reset to the bit sequence and then allow to be sent when load/reset is no longer active. If you need to load different values then you'll need to add some external interface to the outside world e.g. the 16-bit GPIO, switches, a serial interface of some sort. You also need a pin to send the MSB of the shift register out so you can "see" the bit sequence on a scope or logic analyzer. And a debounced load/reset pin for the shift register.

So if you decide to make use of those 16 digital I/O you could have 10-pins for selected bit seqeunce, 1 pin for loading/shifting the shift register, and 1 pin for the output bit sequence.

Unfortunately given my assessment of your ability, I get the feeling that my comments above are only going to produce an excessive number of requests for hand holding through every aspect of designing this.

Regards

- - - Updated - - -

Because it took only 2 minutes to write....
Code: 
module bit_seq (
  input         clk,
  input         load,
  input [9:0]   sequence,
  output        bit_sequnce
);

  reg   [9:0]   sreg;

  always @ (posedge clk)
    if (load) sreg <= sequence;
    else      sreg <= {sreg[8:0], 1'b0};

  assign bit_sequence = sreg[9];

endmodule

Note: I didn't do anything to synchronize the load input to the clk.
 
Hi Ads-ee

sorry to disappoint you but yes I am starting from the basics. Just a last question that can I specify some 16 bit pulse train like "1011001011001010" in the Xilinx ISE software and with the on board clock that I have can I have this pulse train output serially on the one pin of the FPGA which I can observe on a scope ? So basically I don't want to provide any input (like input[9:0] sequence as you have done in the module above) except clock and load then have this 16 bits (with min pulse width = 30 ns) go to one of the IO pins on the kit.

I am really grateful to you for being responsive and patient with me. It would be very kind of you to respond to my query above.

Thanking you
Regards
 

Cookies on standby...

Oh what the hell. typing challenge. Budget is 60 seconds, starting ... now:


Code Verilog - [expand]
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module bit_seq (
  input         clk,
  output        bit_sequence
);
 
  reg   [9:0]   sreg = 10'b1110110011; // <== fill in proper pattern yourself. Only 60 seconds
 
  always @ (posedge clk)
      sreg <= {sreg[8:0], sreg[9]}; // <== will cause repeating pattern of 10 bits long
 
  assign bit_sequence = sreg[9];
 
endmodule


Crap! 80 seconds. And now more since I had to edit as well. Oh well...

- - - Updated - - -

Also, before you come up with more questions ... may I suggest you put this code through a simulator so you see what is happening? That also makes it easier for you to make small changes, and see how that affects the output.
 
Last edited:

Here is an improvement to allow you to see the pulse sequences in the simulation, so you don't end up with a horrible run-on pulse train

Typing challenge <80 seconds:
Code Verilog - [expand]
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module bit_seq (
  input clk,
  output bit_sequence
);
  reg [19:0] sreg = 20'b1110110011_0000000000; // use your own 10-bits value
 
  always @ (posedge clk)
    sreg <= {sreg[18:0], sreg[19]};
 
  assign bit_sequence = sreg[19];
 
endmodule

Darn took me 2 mins...I should have used VIM and copied it (editing all the j/k/l/h/o/y etc took a lot of time :-( )

Regards

- - - Updated - - -

VHDL version

took me 4 minutes to type it (I don't use VHDL much)

Code VHDL - [expand]
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entity bit_seq is
port (
  clk : in std_logic;
  bit_seqence : out std_logic;
);
end bit_seq;
 
architecture behave of bit_seq is
  
  signal sreg : std_logic_vector(19 downto 0) := "111001100110000000000";  -- use your own 10-bits value
 
  process (clk)
    if rising_edge (clk) then
      sreg <= sreg(18 downto 0) & sreg(19);
    end
  end process;
 
  bit_sequence <= sreg(19);
 
end behave


Interesting statistics on the two versions:
removing all CR and joining all the lines of the code into a single line with space between statements:
VHDL: 357 characters
Verilog: 221 characters
No wonder it takes longer to type besides my lack of using it.

Lesson to be learned here...If you have or are starting to get carpel tunnel use Verilog! ;-)
 
Last edited:
ads-ee said:
took me 4 minutes to type it (I don't use VHDL much)
...

No wonder it takes longer to type besides my lack of using it.

Lesson to be learned here...If you have or are starting to get carpel tunnel use Verilog! ;-)
Click to expand...

Heh, 4 minutes is not bad. I would probably take a whole lot longer, my VHDL is mainly read-only... And since using system verilog my period urges to learn vhdl have been pretty much taken care of. *phew*

Anyways, hopefully the OP will be able to testbench it and play around with it to see how things work.
 
Hi

Thank you everyone for responding and being patient with me.
Simulated and its working. Will create TB now.

Is there any good book that you can suggest for digital circuits(possibly available online) which I can read to enhance my understanding and to make my concepts more clear.

Thank you
 

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