preethi19
Full Member level 5
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Hi i need to generate 2 pulses. I need to clock the pulses in a way that when the signal "level" is asserted pulse 1which is normally low becomes high for 2 clock cycles while pulse 2 which is normally high becomes low for 1 clock cycle. Can anyone please help me with a sample vhdl code from where i can build it myself. Thanks a lot!!!