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for me the simplest approach would be to increase the LFSR bit width.

Now it is 9 bits.  usable numbers 1...511

You can just make it 24 bits wide (ant the seed also 24 bits) ... and use any 9 bits you like to.

Then you have 15 redundant bits making 32768 different orders of the random numbers.

There are other approaches (with god and bad) ... it is just an example how to improve the existing system on randomness.

And these 15 additional bits really don´t cost much of an FPGA´s resources.

Klaus