library IEEE;
use IEEE.std_logic_1164.all;
entity offset_generator is
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
seed : in STD_LOGIC_VECTOR(32 downto 0);
result : out STD_LOGIC_VECTOR(10 downto 0)
);
end offset_generator;
architecture offset_generator of offset_generator is
signal s_result : STD_LOGIC_VECTOR(10 downto 0) := (others => '0');
type t_int_array is array(natural range 0 to 360) of natural range 0 to 1436;
constant possible_values : t_int_array :=(4,8,12,16,....,1432,1436);
signal s_seed : STD_LOGIC_VECTOR(32 downto 0) := (others => '0');
function GET_RANDOM (seed : in STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return INSERT_IMPLEMENTATION_HERE;
end;
begin
result <= s_result;
process( clk )
begin
if (rising_edge(clk)) then
if (reset = '1') then
s_seed <= seed;
else
s_result <= GET_RANDOM(s_seed);
end if;
end if;
end process;
end offset_generator;