Generate mamping for verilog HDL

rajavel.rv · May 8, 2014

Generic mamping for verilog HDL

Hi, how can am a passing a separate constant value to my verilog module in my top level of coding; if am using VHDL means i can use this syntax;

VHDL;
example;

entity entity_name is
generic (
K_CONSTANT : integer := 6
);
port (
);

if am port mapping this code means am using this syntax;

c1 : entity_name
generic map( K_CONSTANT => 5)
port map (

);

how can am use this type of syntax in verilog hdl; please send the syntax of verilog hdl;;;;

Regards
rajavel.rv

kommu4946 · May 8, 2014

In verilog you can pass parameters in this way...

Code:

module module_name #( parameter k_constant=6)
           ( input ,
              output ports);

module_name #(.k_constant(5)) c1
              (.in(in_port),
               .out(out_port...);

Generate mamping for verilog HDL

rajavel.rv

Member level 3

kommu4946

Member level 4

rajavel.rv

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Generate mamping for verilog HDL

rajavel.rv

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