[SOLVED] generate for loop inside a generate if loop

[anusha vasanta]

Hi all,
can we use generate for loop inside a generate if loop which is outside of my always block, basically i want some instantiation using my for loop and here i had a register which i need to control using my if condition. that register will take a general value in my first for loop condition like i=0 and for remaining i values it will take value of instantiation result into my register . so here i need to ctrl my register.
anyone help me.
thanx in advance

 

[rberek]

Hi

You still don't sound like you grasp what a generate statement is used for in Verilog. For most designers, these are not frequently used.

Generate statements exist to a) save you from having to repetitively type similar states and/or b) having the ability to conditionally add code to your file.

It sounds like you want to use generate to save a pattern to a register. You can't do that with a generate statement.

If you created the following generate block:

[syntax=verilog]logic   [1:0]       blah;

genvar i;

generate
   for (i =0 ; i<4; i++) begin
    assign blah = i;
endgenerate[/syntax]

This is the code that will be used by the simulator or synthesizer:

[syntax=verilog]   assign blah = 0;
   assign blah = 1;
   assign blah = 2;
   assign blah = 3;[/syntax]

And the only value that will be assigned to blah, assuming the simulator or synthesizer doesn't complain about it, is 3, since that is the last assignment made to blah.

More to the point, you imply that you want to repetitively assign values to a register outside of an always block. That is not valid Verilog.

If you need to store an internally-generated pattern to a register, you will need to feed that register with the output of a lookup table, an FSM , a counter, etc. that you design. And do that in a sequential always block.

As has been suggested previously, you may want to get a good textbook and Verilog and look for templates for registers, etc.

r.b.

 

[mrflibble]

You still don't sound like you grasp what a generate statement is used for in Verilog. For most designers, these are not frequently used.

...

As has been suggested previously, you may want to get a good textbook and Verilog and look for templates for registers, etc.

Indeed. For a quick overview, see the Generate block section (page 21+) of this pdf: **broken link removed**

 

[anusha vasanta]

thanku all for ur valuable guidance.
1.what my doubt is can we write a for loop inside a generate if condition?

2.if i had a code of multiple assign statements with in a generate block the result of first one is depending on 2nd assignment then how will be the order of execution take place.

3. can i write an assign statement and multiple instantiation using gen for block and both are interdependent on one another

suggest me thanku ..

 

[mrflibble]

Just Read The FIne Manual, and you can answer all this for yourself. 1) yes 2) dunno, question too vague. 3) possibly, but again too vague. And 4) now go read it already, because you will just ask more followup questions.

 

[rberek]

2.if i had a code of multiple assign statements with in a generate block the result of first one is depending on 2nd assignment then how will be the order of execution take place.

Assign statements have no order of execution. They all take place simultaneously and at time 0.

r.b.

 

[FvM]

The question still has a certain vagueness. It would be better to clear your thoughts and write down a few lines of code that show what you want to achieve. This would give you also the chance to test syntax legality by sending it to a synthesis tool or simulator.

 

[mrflibble]

Assign statements have no order of execution. They all take place simultaneously and at time 0.

Yup. I strongly suspect anusha vasanta is thinking in terms of imperative programming (sequential execution) as opposed to unrolled logic that is executing in parallel. Which is why I keep pointing in the direction of "Read THAT first". Because the first step is to get rid of incorrect assumptions about what a generate statement actually does. Understanding that will magically take care of question 2 and 3.

 

[ads-ee]

Yup. I strongly suspect anusha vasanta is thinking in terms of imperative programming (sequential execution) as opposed to unrolled logic that is executing in parallel. Which is why I keep pointing in the direction of "Read THAT first". Because the first step is to get rid of incorrect assumptions about what a generate statement actually does. Understanding that will magically take care of question 2 and 3.

If you look back in their post history, most of the problems they've had are all rooted in the difference between HDLs describing hardware and their imperative programming thought process. anusha vasanta has a great big software hammer and anything that looks like "software code" is a nail. ;-)

 

[anusha vasanta]

thanks all,
i am a new learner not a s/w hammer.thanks for all all of your suggestions.