General System Design Question (XPS and ISE)

General System Design Question (The link between XPS and ISE)

Hii Guys,

Sorry if it sounds some how a stupid question but am still a beginner and I need to get things clear.

Im using a Virtex 5 FPGA and trying to build a digital system which implements an algorithm. For this algorithm to be implemented in a correct way, I implemented around three different cores using VHDL and the ISE tool. I also need to access the compact flash memory found on the board to load some bits which I will previously store(as data to be processed) to be able to start the processing.

I cant figure out how to integrate the whole system together in the XPS!. My VHDL cores would start working once I enable each one of them through the Enable pin (That was through implementing test benches for each of them and checking that they are working correctly). My question now is how can I integrate the whole system together? I am missing the link between the VHDL cores I created and the XPS software.

One thing I should do(I guess!) is to define my VHDL cores as IP cores in the XPS..but then what? how can I control these IP cores and how can I enable each one of them in the correct order or when data is available to it.

Is this done through C code?..if yes where should I write it.

I would appreciate it if some one can provide some tutorials or examples for small systems to have a clear view of the thing.

Eshbon.

You need to use both vhdl and C to create an interface. There are examples in the installation in how to setup a core within XPS. I haven't used it for a long time but I recall in the Virtex 2 Pro using the PowerPC, you have to use the OPB bus to talk to your peripherals (that is your core). From my previous experience, you would have to create a .mpd.pao file and userlogic.vhd. The pao file is used for describing the ports, mpd file is used for the compilation list. From XPS, you have to create a custom peripheral and select the bus the core is using. To communicate between software and hardware, you would have to use software registers, FIFOs, interrupts. The user logic is the interface to registers FIFOs etc..
The other thing you would have to do is to setup the base address of the peripheral so the software can access based on the base address. You need to check the examples in how the address are setup as I can't remember.

Here is some block diagrams of some of my designs which I drawn out a while back so you can get idea how the peripherals are joined. I think there should be enough information for you to investigate further in how to design a custom peripherals. I kind of miss using FPGAs :-( but I do have XUPV2P board lying around which I can play around with. I imagine it has change quite a lot since Xilinx started using the ARM processor but the interface should be similar. I believe the same idea applies to Altera Nios.

Heey eziggurat...thanks alot for ur reply and the block diagram u attached as well...its really helpfull.

I have a question concerning the "software registers" which should be used as an interface between the C code and my peripheral(as much as I do understand).

The question is: lets assume I have a core(peripheral) that does some calculations on a picture that contains a huge number of pixels (more than 160,000). the calculation is carried out on each 15 bytes of the total number of bytes.

I will create an array with the 160,000 pixels in the C code. My idea is to have 15 software registers(one register for each pixel) for my VHDL implemented core. My question is how to feed the 160,000 pixel (15pixels at a time) to the 15 software registers using the C code? In other words, how can I force the C code to follow my scheduling of the core (feed the first 15 bytes, wait for two clock cycles which the core needs to do the calculation and then feed the next 15 pixels and so on).

what I have in mind is to loop over the array and feed 15 bytes by 15 bytes till the end of the array, but again how can I synchronize one feed of data to the 15 software registers with the clock of the system!

Hope its clear what I need to understand

eshbonzie said:

Heey eziggurat...thanks alot for ur reply and the block diagram u attached as well...its really helpfull.

I have a question concerning the "software registers" which should be used as an interface between the C code and my peripheral(as much as I do understand).

The question is: lets assume I have a core(peripheral) that does some calculations on a picture that contains a huge number of pixels (more than 160,000). the calculation is carried out on each 15 bytes of the total number of bytes.

I will create an array with the 160,000 pixels in the C code. My idea is to have 15 software registers(one register for each pixel) for my VHDL implemented core. My question is how to feed the 160,000 pixel (15pixels at a time) to the 15 software registers using the C code? In other words, how can I force the C code to follow my scheduling of the core (feed the first 15 bytes, wait for two clock cycles which the core needs to do the calculation and then feed the next 15 pixels and so on).

what I have in mind is to loop over the array and feed 15 bytes by 15 bytes till the end of the array, but again how can I synchronize one feed of data to the 15 software registers with the clock of the system!

Hope its clear what I need to understand

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