gatedriver
Junior Member level 1
Dear all,
Thanks you everyone who help me about convergence problem. But, unfortunatelly, when I am not success to fix this problem the others come.
This time is:
Overflow, Convert
INTERNAL ERROR -- Overflow, Convert
Run aborted
Disk write error. The disk may be full.
ERROR -- Disk write error. The disk may be full.
So I have some questions:
1. In the features of IR2113
( 3.3V logic compatible; seperate logic supply range from 3.3V to 20V)
I understood that IC can be compatible with DSP output signal (3.3V)
But in the Static Electrical Characteristics ( VIH-logic 1 input voltage is 9.5V; VIL -logic 0- is 6.0V)
So I decided choose PWM pulses is 15V. Is it correct? What are the functions of VDD logic supply?
And the second is COMP block in IR2113 pspice model
.SUBCKT COMP 1 2 3 4
E1 5 4 VALUE={IF((V(1)>V(2)), V(4)+5V, V(4))}
R1 5 3 1
C1 3 4 10P
.ENDS
How can I use this block? Is it relate to my internal error?
I posted my circuit here? I really need helps from everyone
Thank you very much!
Thanks you everyone who help me about convergence problem. But, unfortunatelly, when I am not success to fix this problem the others come.
This time is:
Overflow, Convert
INTERNAL ERROR -- Overflow, Convert
Run aborted
Disk write error. The disk may be full.
ERROR -- Disk write error. The disk may be full.
So I have some questions:
1. In the features of IR2113
( 3.3V logic compatible; seperate logic supply range from 3.3V to 20V)
I understood that IC can be compatible with DSP output signal (3.3V)
But in the Static Electrical Characteristics ( VIH-logic 1 input voltage is 9.5V; VIL -logic 0- is 6.0V)
So I decided choose PWM pulses is 15V. Is it correct? What are the functions of VDD logic supply?
And the second is COMP block in IR2113 pspice model
.SUBCKT COMP 1 2 3 4
E1 5 4 VALUE={IF((V(1)>V(2)), V(4)+5V, V(4))}
R1 5 3 1
C1 3 4 10P
.ENDS
How can I use this block? Is it relate to my internal error?
I posted my circuit here? I really need helps from everyone
Thank you very much!