Gated Clock: why using of Latch is preferred over using a FlipFlop

[ivlsi]

Hello All,

Why using of a negative edge Latch is preferred over using a negative edge FlipFlop for gated clock controls?

Thank you!

 

[krishna2728]

Gated clock is a well known method for reducing power consumption in synchronous digital circuits.By this method the clock signal is not applied to the flip flop when the circuit is in idle condition.This reduces the power consumption.
In a digital circuit the power consumption can be accounted due to the following factors:
1) Power consumed by combinatorial logic whose values are changing on each clock edge
2) Power consumed by flip-flops.
Of the above two, the second one contributes to most of the power usage.
A flip flop consumes power whenever the applied clock signal changes,due to the charging and discharging of the capacitor.If the frequency of the clock is high then the power consumed is also high.Gated clock is a method to reduce this frequency.

https://vhdlguru.blogspot.in/2010/04/what-is-gated-clock-and-how-it-reduces.html

 

[ivlsi]

Thank you for your comments, but my question was a little bit different...

The question was as following: "Why it's better to use LockUp Latches on the Gated Clock Control lines instead of Negative Edge triggered FFs?"

Thank you!

 

[ivlsi]

So, why using latches for controlling the gated clock is better the using negedge flip flops?

 

[Alosevskoy]

One of the reson is that latches smaller then flip-flops.

 

[ivlsi]

latches smaller then flip-flops

It's a minor reason

 

[owen_li]

Hi.
In my opinion, it is mostly because of the timing issue.
If you use negative flipflop, the clock gating enable timing path is just half cycle path ( clock gating check).
However, when using negative latch, coz latch is a level sensitive sequential cells, the clock gating enable timing path will be a full cycle path.
STA tools, like primetime can apply timing borrowing on this clock gate latch when performing clock gating check.

Thanks!

 

[yawnspring]

Hi,
Latch can remove the glitch at clock signal.

Thanks!

 

[ivlsi]

Latch can remove the glitch at clock signal

How? Cannot a negedge flop do the same?

---------- Post added at 14:39 ---------- Previous post was at 14:31 ----------

when using negative latch

I think we use high-active latches for the gated clocks since low-active latches don't prevent glitches on the clock (in case the propagation delay of the clock gating logic is bigger than a clock cycle).

 

[ivlsi]

Hi All,

As for the Gated Clock, why is Latch preferable over Flop for gating the clock?

Thank you!