iamxo
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such as in the MDAC circuit (in pipeline ADC), in sample phase the voltage at opamp input is charged to Vcm, then in the hold phase what is the voltage value at this node? still Vcm?
In my transistor level circuit simulation, in sample phase it's 1.5v, however in hold phase it decreases to 1.43v, how does this happen? anyone help me, thank you in advance.
Or Does any material talk about this?
In my transistor level circuit simulation, in sample phase it's 1.5v, however in hold phase it decreases to 1.43v, how does this happen? anyone help me, thank you in advance.
Or Does any material talk about this?