Gate-Source Signal

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matrino

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Figure 1: The Schematic

This is my buck converte schematic. I have designed to manage 24 watt (2 amper output),but I have a problem. The problem is the gate-source signal not proper and the circuit not working that I designed. When there is no load the output voltage is good (12.5V). If I connet a load the circuit, the circuit not working and the output voltage drops. Sometimes can maange 0.2 amper at 12.5 V, but If I reduce the load resistance value the circuit give zzzz sound (from tps40200) and the output voltage reduces. I think the problem cause the source-gate signal. I added the oscilloscope fotographe.

Figure 2: Source-Gate signal (pmos)
 

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If the output switch is PMOS then the gate waveform is "mostly on" when it should be about a 30% duty cycle.

That's not right. Can't see Y axis to judge further about levels etc.
 

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I wonder how Vsg is limited in the IC. The example shows a 12V Zener shunt.


Your plot 5V/div, shows 3 to 8V and Vt= 1 to 3V, so why is it not getting at least 4.5V required makes me suspicious the GS is damaged
Verify the 40Vin and also the surge current on startup for the load.
 

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