gate pin pushed below gnd in smps

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eem2am

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smps pin details

hello,

do you believe this boost needs a schottky diode from gnd to gate?

this boost is 12 to 28v @10w.

because if such a schottky is not added -then when the fet turns on the drain-gate capacitance will push the gate pin below ground?

 

smps pin

when the fet turns on the drain-gate capacitance will push the gate pin below ground
Click to expand...
Sounds very unlikely. Did you observe any problems?
 

12 pin at details of smps

well...some controllers have failed for unknown reasons.

its just that adding the said schottky is "par for the course" with offline smps's, so i thought it may still apply, to some extent with low voltage converters such as this.

its the old principle that you dont tend to change the voltage across a cap instantly....so if the drain suddenly drops from 28v to 0v when the fet turns on.....then the gate MUST drop from 15V to (15-28) = MINUS 13V.

...due to the drain_gate capacitance
 

14 pin smps

I can't follow the explaination. Because the FET is driven from the gate, Cgd acts as a negative feedback (miller capacitance)
that doesn't allow the gate voltage to fall below the threshold voltage in on state. Also the driver impedance and gate resistor
dimensioning are against this possibility.
 

gate pin

It depends on the controller ,in the datasheet SLUA178 they specificly mention this problem .
This is later solved by either including the shottky in the controller or instead of transistor totempole a mosfet totempole.
You can actualy destroy controllers cause with the polarity reversal parasitic connections can open between the substrate of the chip and the semiconductor .
(sorry if my explanation is a bit haphazard)
This effect is described in the unitrode datasheets and the seminars from texas instruments .
Shottky's can prevent this from happening ,more modern controllers don't need that anymore usualy .

Good luck .
 

smps which is ground pin

I don't doubt, that forward biasing of substrate diodes can cause latch-up and possibly damage of a chip due to high latch-up currents. Latch-up immunity is mainly achieved by suitable chip design, schottky diodes aren't provided by usual analog processes as far as I know.

But I don't see, how the presented circuit can produce negative voltages at the gate drive output that bring up latch-up.
 

smps pins description

Page 12 , figure 9 of this

**broken link removed**

..says why this schottky is needed. and it explains the negative voltages.
 

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