Gate Oxide thickness of Transistor

Hai friends,

Is there any difference bw physical oxide thickness and Effective oxide thickness (EOT)?

pls clarify my doubt...:thinker:

See this BSIM manual: View attachment BSIM480_Manual.pdf , p. 11

Here is my understanding:

- physical oxide thickness is the real thickness of the gate dielectric layer, that you can measure with a ruler on TEM vertical cross-section.

- effective or electrical oxide thickness is the thickness of SiO2 layer that would produce the same capacitance (per unit area) as the given technology. There are several reasons why this thickness may be different from the physical thickness:

(a) gate depletion effect and quantization of the carriers in the channel - lead to effective increase in gate oxide dielectric (depletion region thickness plus distance from the SI/oxide interface to the peak carrier concentration in the channel)

(b) material having higher dielectric constant than SiO2 (like nitrided oxides, or high-K materials) lead to decrease of effective oxide thickness.


Finding a clear straightforward explanation in BSIM4 user manual is not an easy task - can someone point to the page/paragraph detailing this?

There are several ways to measure the feature, but for the
model you want the one that is closest to electrical (rather
than, say, optical) realism.

Of course when you have effects like poly depletion in play,
there may not be a single right answer (poly depletion being
itself, bias dependent and swinging the Cox independent of
how the channel is being swung meanwhile).

This is why all the knobs on an empirical model - too many
realities to stay with simple mathematics anymore.