Gate Oxide Breakdown Voltage

[ee_expert2000]

gate oxide breakdown

I am using nmosmh4 from PRIMLIB in Cadence Virtuoso.
when I am simulating the desgin, a warning shows up saying:
"Vgd has exceeded the oxide breakdown voltage of `vbox' = 15.14 V"
this warning dispappears when I decrease my transistor size but I need to have a very large tansistor
for a power amplifier design.
How can I have a large transistor without this warning?
What is the Actual cause for this?
Any hint or help???
Regards

 

[lavitaebelle]

oxide breakdown voltage

The warning message means that your gate drain voltage is exceeding the limit allowed for gate oxide breakdown. Usually in a design care must be taken such that Vgd must not supposed to exceed the nominal supply voltage for the technology. The limit is around twice the supply.

In CMOS PA design, the gate oxide breakdown is one of the biggest challenges. This reduces the swing at the output and limits the output power level.

By reducing your transistor size, you have reduced the gain and hence the swing at the output.
Do your sizing,biasing,matching such that you dont exceed the breakdown limit.

 

[piao]

gate oxide breakdown voltage

lavitaebelle give you the good explanation, actually it depends on the different processes.

anyway a designer should keep in mind there is physical limitation for design.

 

[sunking]

oxide breakdown

add a protected circuit(diode and so on)

 

[jcpu]

vgd breakdown voltage

Casecode mos can effectively aborb excessive Vgd.

 

[mithlesh]

vgd breakdown

use DGO devices, if technology permits. These devices have higher gate-oxide breakdown voltage.

Mithlesh