Gate level simulation

[amansingh2704]

I have few question regarding Gate Level Simulation.
1. what is difference between power aware netlist and non PA netlist.
2. Does Non PA netlist contains low power element such as clock gating, isolation, retention cells etc. ?
3. Do we run PA sim with SDF? In real chip we will have power as well as delays, so running PA+SDF makes more sense(my thinking)
4. Does STA engineer checks multi-cycle path and false path?
5. Once PA sim is completed, what do we check?
6. while running PA-GLS, if we forget to add power pin (vcc,vss) in UPF for a particular partition, we will get x in all outputs after simulation. is it possible to check and cure this issue after build is completed?

 

[D.A.(Tony)Stewart]

1. a non-PA netlist does not contain this specific power-related information.
2. It may include logical functionality but not compute I^2*RdsOn*t/T for energy or average power and thus temperature rise results and the effects.
3. yes PA + SDF to simulate power effects on delays
4. yes "STA Engineers" verify multi-cycle paths and false paths with 4 corner temp with Vdd variations, yet slowest is hot -10%Vd and fastest is cold -10%Vdd
5. margins to failure for yields (Cpk), Pd & distribution across domains, heat distribution design techniques, then maybe crosstalk susceptibility, Vdd, Vss noise Vpp % with noise injection tests, with clock tolerances xx ppm or x % if internal. (Once called Schmoo tests)
   1. Then prepare DVT report to report results with measured margins & conditions on all critical specs. e.g -10%Vdd @ 70'C max speed with/without injected ripple on Vdd.
6. yes update UPF then rerun.

A DVT report is vital for tracking and reporting the design's performance and compliance with specifications.

 

[ThisIsNotSam]

I have few question regarding Gate Level Simulation.
1. what is difference between power aware netlist and non PA netlist.
2. Does Non PA netlist contains low power element such as clock gating, isolation, retention cells etc. ?
3. Do we run PA sim with SDF? In real chip we will have power as well as delays, so running PA+SDF makes more sense(my thinking)
4. Does STA engineer checks multi-cycle path and false path?
5. Once PA sim is completed, what do we check?
6. while running PA-GLS, if we forget to add power pin (vcc,vss) in UPF for a particular partition, we will get x in all outputs after simulation. is it possible to check and cure this issue after build is completed?

1 - terminology is critical here. I am not 100% sure what you mean by power aware netlist. In some PDKs, you get two versions of a cell definition, one with .VDD/.VSS pins and one without. They are useful for LVS, but have zero impact on power calculation. Is this what you mean by PA netlist?
2 - clock gating is present on the netlist if it exists on the design. there is nothing special about it. It is a logic cell, after all. ISO and retention cells can be modelled in strange ways. You would have to check what your PDK offers.
3 - with any netlist, if you want better power estimate, SDF itself is not enough. You also need VCD. As you hint at, the more details you provide, the better power estimates you will get. Specially if you are doing dynamic power checks instead of average power.
4 - Kind of vague question. STA engineer has to work with RTL team to understand where MCPs and false paths are located and whether they really can be used.
5 - Well, the flow goes on, You still have LVS, ERC, DRC, LEC, and so on.
6 - UPF file is, generally speaking, not simulatable. It is used to give the tools some high level understanding of your power considerations. The netlist generated is influenced by UPF and it is the netlist that will be simulated. If the netlist is generated correctly, it will be fine. If the pin is forgotten, it will not be fine (see answer to #1). Can be fixed by regenerating UPF and regenerating netlist. Can be scripted externally too if needed for some reason.

 

[D.A.(Tony)Stewart]

Especially in mobile applications, PA-GLS is done earlier to find opportunities before expensive stages of the design flow.