Gate level logic simulation

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Yuya_O

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In gate level logic simulation, I use +no_notifier option to suppress that propagating X value to latter logic circuit. If I use this option and timing error happend, then the X value turned 0 or 1 randomly not to propagating value ?
I'm using VCS for this simulation.
 

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It should not be random. Check the simulator's documentation and check your verilog model of your flip-flop to understand how the timing checks are coded.
 
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