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Hi,
Do you know which of the attached winding configurations would give least leakage inductance for a 1:1 gate drive transformer?
(For Hi side fet of 2 transistor forward, 390VDC input)
Thanks yes,
Ill do it on ungapped an E16/8/5 core using Ferroxcube 3F3 ferrtie (Fsw = 80kHz)
3 layers of secondary (each 23 turns of 34SWG ECW)
2 layers of primary (each 34 turns of 30SWG ECW)
...All interleaved
make sure you have 1kV of functional isolation ...
given the above, and say 15V sec, 50% 80kHz the B swing is +/- 88mT ( good) and the L pri is ~ 1.1mH, assuming 22V of drive on the higher turn pri the I will be +/- 60mA pk + gate drive peak currents ...
However it is better to have the 3 wdgs as the primaries - as they are the driving wdgs, and the 2nd-aries as the two wdg output - as they are firmly coupled to the primaries - and not vice versa as you have penned it ...
Thankyou, BTW, the attached is now the intended winding configuration.
In this way, i presumed it was OK to have either winding as the pri/sec?
Regarding the 1kV of functional isolation, i had hoped to get away with plain ECW for the first prototype. A winding co once told me that this is good to 1kV...
Series connection of the partial windings will probably introduce additional leakage inductance due to different winding diameters, parallel connection would be preferred.
Interwinding capacitance and isolation requirements are reasons to use fewer partial windings.
OK - series connection is OK - not quite as good as parallel connections
grade 2 ECW means nothing to me - is it a solderable PUR I or II or PEI 180 deg C rated? it may work to 1kV - but if you nick it while winding - all bets are off ...
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