gate coupled NMOS as power clamp???

[prcken]

gcnmos

Hello,
I have a question about gate-coupled NMOS for ESD protection. Usually the GCNMOS is used as power clamp between VDD to VSS. P+ poly resistor and MOS capacitance are used to set the RC time constant to sense the ESD stress to help triggering the NMOS clamp, so, when you design this RC triggering circuit, how much voltage do you expect appear at the triggering node (the gate of the NMOS device)??? I know the RC constant should be slower than the rise time of the ESD pulse (e.g.10ns), and faster than the rise time of normal operation voltage (e.g. 1ms). But, I think more than that!!! I mean the triggering voltage at the gate should be set just more than the threshold voltage of the NMOS device. However, even if you set the RC time constant at µm range to meet the above statement, the triggering voltage can easily follow the stress reaching more than 10V, does that mean it threatens the gate oxide reliability???
regards!
Kehan

 

[srftech]

gate coupled nmos

Hi Kehan,
It sounds like you are confusing the difference between a snapback based Gate-coupled NMOS (GCNMOS) and a MOS conduction Based "Active Clamp" or "Big FET" nmos, to use terms common in the industry.

For a GCNMOS, your only goal is to allow the gate voltage on your clamp to rise just above Vt. It does not need to remain much higher than Vt, even for the duration of the ESD event, only long enough to allow the gate voltage to rise and help trigger the snapback of the clamp. So when designing this, what your are really looking for is to capacitively couple 1-2V to the gate, but not allow the gate to get much higher than that, because as you pointed out, you do not want to threaten the oxide integrity. The only point here is that having a slight voltage on the gate lowers the snapback trigger voltage below, what is normally the avalanche threshold of the drain and it also allows for better multifinger triggering, as opposed to normal snapback which can be limited to one or two fingers, reaching failure before invoking the full power of the clamp.

Generally, you can leave the RC in the low nS range for a GCNMOS. I can not give you an exact number because that is part of the art and science of designing a good clamp and much depends on both your process, your product targets and your clamp design itself.
As for how much total voltage appears, well that depends, not only on the capacitance and coupling, but also on the ESD current your targeting and size of your device. Consider also than many oxides can tolerate voltages well above their DC failure, for a few 100nS's. Remember too than an HBM event may be a few 100nS';s, but a CDM event will come and go in less than 5nS-10nS max, make sure your clamp will trigger in that time!!!

 

[prcken]

gcnmos gate voltage with time

Hi Kehan,
It sounds like you are confusing the difference between a snapback based Gate-coupled NMOS (GCNMOS) and a MOS conduction Based "Active Clamp" or "Big FET" nmos, to use terms common in the industry.

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yes, i was confused by the GCNMOS and Active Clamp
i treated this two as one thing before