gate count in the synthesis report in xilinx

Status
Not open for further replies.
J

jincyjohnson

Member level 4
Joined
Aug 24, 2013
Messages
72
Helped
1
Reputation
2
Reaction score
1
Trophy points
8
Visit site
Activity points
436
During synthesis in xilinx, i got number of slices,slics flip flop, 4 input LUT's, bonded IOB's GClk's. How can i get the number of gates. plz reply
 

using the slice, flip flop and lut count.
 

    V

    Points: 2
    Helpful Answer Positive Rating
jincyjohnson,

If you need to come up with some translation method you might want to try getting a hold of the originator of the following thread.
https://www.edaboard.com/threads/298717/

They were working on a tool to estimate utilization based on a gate-like model for FPGAs.


Regards
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…