Gate Count / Gate Systhesis Methology or Design Flow

[syhsim]

Hi,

Im under an research on:
1) How to do the gate count from a set of HDL code / Macros?
2) What is the gate systhesis methology or design flow?

appreciate that can share with me the resources of the info.
thank your very much!

regards,'
yh

 

[Arik]

Hi syhsim

You can find gate-numbers for a set of HDL code in the area reports resulting from logic synthesis of the design represented by the set of HDL code. Actually, design area is expressed in area reports by means of square microns. So , in order to get the gate count you need to divide the design area to the area of a 2 input NAND gate from your synthesis library.

For example, if the design area found in area report is 15000 um^2, and the area of a 2 input NAND gate in your synthesis library is say 5.2 um^2 then the gate count will be 15000/5.2 ~ 2884 gates.

 

[syhsim]

Hi,

Thanks for your reply.
Im looking for the methology of gate calculation / or do have any standard libaray for it?
Example with an HDL code as below with a Macros function ADD,

architecture ADDER of A_design is
begin
ASYNCHRONOUS_State0_SM : process (A,b,c)
begin
X <= "00";
X <= ADD (A,b,c);
end process ASYNCHRONOUS_State0_SM;
end ADDER;

then im intrested to know what is the actual gate will be systhesis? and if the design go more comple, what is the logic gate / register will be systhesis...

Best Regards,
syhsim

 

[Arik]

Generally there is no any standard methodology for gate-count calculation. For macros usually you can find area info in the macro's datasheet. And for any HDL code to estimate gate-count there are 2 main apporaches:

1. Logic synthesis
2. High-level (RTL) estimation methods.

Estimating gate-count via logic synthesis is accurate and you get the exact number of gates of your design. High-level estimation, generally, provides 15% to 25% accuracy compared with logic synthesis but is much more faster.

So you can choose the type of estimation you need.