GaN transistor iv Measurement Method Question

[hunas2127]

I measured the results by sweeping the gate voltage from -4V to 0V using the pulse mode of the SMU. Current collapse occurred due to the self-heating effect. What can be done to measure correctly? The on-wafer probing was performed on a cu heat sink.

 

[dick_freebird]

Pulsed mode

 

[BigBoss]

Where did you use Pulsed Mode Voltage on Drain side or Gate side ?
To my knowledge, a pulsed mode voltage should be used at Drain side while gate voltage is constant/variable.

 

[dick_freebird]

I think the pulsed mode particulars want a look, and maybe want varied for iso-power (average) as proxy for iso-temp; adiabatic pulse widths so maybe PFM rather than duty per se. If you were patient and acquired settling time (w/ fixturing and harness) fast you could approach known "where it counts" temp experiment conditions, maybe lose some "heat kink" and even not-permanently-drift samples. Though some could be sacrificed in limit-learning.

 

[hunas2127]

Where did you use Pulsed Mode Voltage on Drain side or Gate side ?
To my knowledge, a pulsed mode voltage should be used at Drain side while gate voltage is constant/variable.

Both gate and drain were swept in pulse mode.
The setting values are as follows.
Source Delay: 0.5s
Pulse width: 0.005s
I used the B2902A SMU and Quicky IV measurement software.

 

[dick_freebird]

What is the lowest pulse width that delivers
repeatable accuracy, according to the SMU
docs?

Set up with a pulse generator / slammer
and 'scope and current sense, observe
the thermal time constant / time to get
those undesired effects in full bloom.

 

[D.A.(Tony)Stewart]

Did you have a active load on flying probe probe pairs and then step Vdd while pulsing Vgs on very low pw50 and low duty cycle between gate steps with a pulse.
Or did you use a S&H & reset cap load to measure Id from CdV/dt using an active loaded flying probe pair? Or some other method?

 

[dick_freebird]

Copper heat sink is mentioned but not the cooling of same nor the baseplate temp. The thermal path at probe is unknown at chip scale or below unless measures are taken to ensure good contact and transfer. "On" means nothing.

Unthinned wafer can be much worse than the final-thickness die that will get packaged or mounted in a hybrid, for thermals. Thinning post-measurement may also have implications to your capacitance pull accuracy at wafer probe vs the fielded device.

Also missing here is anything about whether device ratings are or are not respected. The current collapse says "no". Getting the dimensions of wrongness correctly and completely understood should precede test method cut-and-try on the forcing end.