GaN MOSFET vs SiC MOSFET vs Silicon MOSFET vs GaN_Cascode_with_Silicon MOSFET

Hi,
Just read 20 articles and still a little cloudy as to what is the real advantage of GaN MOSFETs.

First of all I’d say that enhancement mode GaN FETs look too dodgy due to too_low_abs_max gate drive voltage concerns. So will only discuss “GaN_cascode” MOSFETs from here on..

GaN has a significantly worse thermal resistance than SiC or Si so I am immediately a little negative towards it.
However, GaN_cascode offers lower rds_ON than SiC.
Also GaN_cascode does not suffer from accidental triggering of the intrinsic BJT. However, neither does SiC.
Also, GaN_cascode does not suffer as much reverse recovery as a high voltage Si MOSFET…but still suffers some reverse recovery due to the low voltage cascaded Si FET.
The advantage of GaN_cascode over SiC seems to be that GaN_cascode can offer higher withstand of high dv/dt?
GaN_cascode also offers lower Cgd than SiC or Si…..but this could be mitigated by a high current gate driver anyway.

So is GaN_cascode’s main advantage in that it can withstand higher dv/dt than SiC? I hear about SiC FETs breaking down in hard-switched converters even if dv/dt on Vds is not that high?

zenerbjt said:

Hi,
Just read 20 articles and still a little cloudy as to what is the real advantage of GaN MOSFETs.

First of all I’d say that enhancement mode GaN FETs look too dodgy due to too_low_abs_max gate drive voltage concerns. So will only discuss “GaN_cascode” MOSFETs from here on..

Click to expand...

I think cascode devices only exist in order to make skeptical engineers more comfortable adapting the technology, even if that mean compromising performance. I guess that tactic works...

GaN has a significantly worse thermal resistance than SiC or Si so I am immediately a little negative towards it.

Click to expand...

AFAIK all GaN devices (with the exception of maybe some RF devices) only use a very thin epitaxial layer of GaN for the active device. Overall thermal performance is dictated by numerous other details.

Also GaN_cascode does not suffer from accidental triggering of the intrinsic BJT. However, neither does SiC.

Click to expand...

GaN FETs do not have the parasitic bjt, since they are HEMTs. SiC FETs are still MOSFETs and thus do still have the same failure mode as silicon devices. However in SiC the threshold voltage of the parasitic BJT is harder to hit, making them more reliable than silicon devices.

As for the other aspects, it's hard to make comparisons without referencing specific devices, or at least concentrating on a Vds range. Packaging is also a huge factor for thermal performance and switching speed.

I haven't seen much of anything about GaN MOSFETs.
Lacking a native oxide, I'd expect much surface state
and bulk trap crappiness (which you also see in SiC
MOSFETs, for slightly different reasons - it's why the
gate range there is -5 to +20V, where silicon MOSFETs
started out that lousy and have improved to the point
that you can get 100V "logic level" FETs. All the carbon
has to go somewhere and it can't, once gate ox has
developed any thickness.

eGaN FETs' gate overvoltage tolerance varies a lot by
manufacturer (as does their honesty about it). EPC
older FETs would suffer a lot with anything over 5.0V.
GaN Systems was claiming 6V rec max. Different
variations on GaN gate structure change what happens
on gate overvoltage, plain Schottky gate vs one with a
P-GaN underlayer are going to be differently robust
(P-GaN underlayer seems responsible for better
overvoltage limit and tolerance to violation).

GaN cascodes should never see the positive overvoltage
scenario as their gate is grounded (to MOSFET source).
One issue is the interplay between "guard" threshold and
leakage floor, and the "switch" MOSFET. The "guard" will
let some leakage; what does the MOSFET do with it, is
pinchoff current of the guard HEMT going to cause an
"off" switch MOSFET to see drain breakdown anyhow?
See in some cases, the cascode center node having
a shunt resistor to ground to keep expected voltage
on the FET drain, tolerable (as long as nothing
unexpected happens). The whole point is to use a low
drain breakdown, low on resistance MOSFET and this
is just waiting for some GaN guard FET degradation
to point out the weakness of the switch FET....

dick_freebird said:

I haven't seen much of anything about GaN MOSFETs.
Lacking a native oxide, I'd expect much surface state
and bulk trap crappiness (which you also see in SiC
MOSFETs, for slightly different reasons - it's why the
gate range there is -5 to +20V, where silicon MOSFETs
started out that lousy and have improved to the point
that you can get 100V "logic level" FETs. All the carbon
has to go somewhere and it can't, once gate ox has
developed any thickness.

Click to expand...

There's no reason to make a GaN MOSFET. If you did, it would no longer be a HEMT, and its performance would suffer.

GaN cascodes should never see the positive overvoltage
scenario as their gate is grounded (to MOSFET source).

Click to expand...

Should also be noted that in a cascode, the GaN device is depletion mode. I wonder if the depletion mode device has better tolerance of gate threshold swing (in both directions) than their enhancement mode counterparts.

My big issue with cascode devices is the internal node (MOSFET drain/GaNFET source) during switching. You just have to trust that this node is going to behave well. Transphorm recommends using ferrite beads and RC snubbers, probably to limit dv/dt on that node. But there's no way to probe that node to verify it.