cupoftea
Advanced Member level 6
Page 22 of the innoswitch3-ep datasheet shows that 150V of margin is recommended between VDS peak and the rated voltage of the GaN FET.
150V margin is never requested for Si FETs. Does this show a weakness to overvoltage of GaNFETs?
Si FETs can reasonably well handle overvoltage ti an extent by just avalanching.
Innoswitch3-ep datasheet
150V margin is never requested for Si FETs. Does this show a weakness to overvoltage of GaNFETs?
Si FETs can reasonably well handle overvoltage ti an extent by just avalanching.
Innoswitch3-ep datasheet