Gain of a Digital circuits/Logic circuits.

Hi
i have adoubt regarding gain..

is there gain available for a digital circuit..

Gain = vout/vin...

then how can we expect gain for a logic circuits..

because in Phase frequency detector circuit.. we consider the gain of PFD to calculate PLL loop bandwidth.

In that case what is meant by PFD gain?
Does it make sense..

thanks in advance

Depends on the PFD type. The gain of a digital PFD can be expressed as vout/input_phase_difference [V/rad].

You can get a -peak- gain but the gain when settled
to the rails is zero. That's called noise margin. Peak
gain will be found at the switching threshold (noise
margin = 0). The DC gain in a PFD is probably not very
interesting, because you're looking for fast edges in
the interest of phase noise and the real gain will be
rolled off from a DC transfer characteristic by the
gates' Miller capacitances.

Hi.. thanks for the replies..

I didnt get the concept yet.. that is explained by dick_freebird...

1)Peak gain.. and gain when settled to rails.. it is a digital circuit.. how can we expect a peak gain other than VDD..

2)you mentioned about noise margin.. can you please explain how noise margin occurs and the effects of noise margin in PFD/whole PLL's performance.

3)and you mentioned about DC gain.. Is it possible to measure DC gain for a PFD.. or any other digital devices..

thanks a lot..

Consider the simple CMOS inverter.

From VIN=0 (VSS) to VT(N) there will be no useful forward
gain at all, the PMOS is fully on and the NMOS fully off so
VOUT moves not at all whether VIN is 0, 0.5V. dVO/dVI is
zero.

Similarly from VIN=VDD0-VT(P) to VDD, except in reverse.
In these deadbands you have great noise immunity.

Between VT(N) and VDD-VT(P) you have some output
response to input voltage. This peaks about VDD/2 (if
you sized the N/P device drives appropriately). As you
near logic threshold, incremental noise could flip the output
and at threshold exactly, your noise margin is exactly nil.
After you cross over, gain recedes back to zero as you
head for the other rail.

Now, every PFD passes through that threshold on every
cycle. Noise is always present to some degree. As you
approach and pass through threshold, along a finite input
dV/dt, noise contributes its own dV in-the-moment and
you transform the noise voltage across the input dV/dt
slope into a "time noise" - jitter, to the digital dude or
phase noise to the RF types - under locked conditions.

You can measure a DC-sweep gain and determine input
noise gain about threshold as a worst case. But you can't
get at the slew rate except by simulation or special test
structures (w/ buffering and maybe varying Cload) because
it is very loading sensitive. The PFD edge rate is one major
contributor to phase noise inside the PLL chip (perhaps, or
not, the dominant one depending on things like VCO Kv,
loop amp & filter noise qualities, IC and board construction
in the respects of EMI self-generation and external pickup).

dick_freebird said:

You can measure a DC-sweep gain and determine input
noise gain about threshold as a worst case. But you can't
get at the slew rate except by simulation or special test
structures (w/ buffering and maybe varying Cload) because
it is very loading sensitive. The PFD edge rate is one major
contributor to phase noise inside the PLL chip (perhaps, or
not, the dominant one depending on things like VCO Kv,
loop amp & filter noise qualities, IC and board construction
in the respects of EMI self-generation and external pickup).

Click to expand...

Hi, Dick freebird.. thanks for your explanation..
i understand the concept of noise in inverter...
so gain means how the noise is converted to a logic level..

Am i right?
and you mentioned about the PFD edge rate causing phase noise..
can you please explain more clearly..?

and how this noises near the threshold region contributes to the phase noise..or jitter?

thanks..

I'm under the impression that the discussion is missing the operation principle of a PLL. The input quantity of a PFD is phase difference not voltage and there's no use of gain specified as vout/vin.

Hi, FvM.. yeah..
But still PFD is one of the noise sources in the operation of PLL ..
Am i right?..

still the noise conversion is a problem in PLL's phase noise and jitter.. am i right..
please explain your point.. about this..
thanks

The gain near threshold of the logic gate, with the supply
voltage, determines the width of the linear input region.
This, with signal risetimes, then determines the maximum
jitter time that can be added / subtracted by noise voltage
superimposed on the input (or supplies). So the gain is not
inconsequential. It may not be a prime target for analysis
as the outcome of interest is the rollup gate switching
behavior, gain and risetimes / bandwidth.

The purpose of Gain in PLL is to analyze Loop gain stability under different conditions.

a Phase detector has a transfer function of k/s, like an integrator, since the integral of frequency is phase and the output , k will be in terms of volts per cycle of phase error. Thus k is usually the mixer voltage with a scale factor of 1/2 or 1 depending on the mixer range.
Mixers that integrate by opening the output with pump up or down use an open circuit and integrate voltage by pumping current according to the phase error, like an integrate and hold circuit.

Although not a perfectly linear system, this method works good for 2nd order systems approximations of overshoot. The frequency part adds stability to the design by switching to a 1st order system with the mixer staying simply hi or low if a gross frequency error is detected.

But digital PFD type II detectors are also more sensitive to phase noise and add more jitter to the clock control voltage.

SunnySkyguy said:

The purpose of Gain in PLL is to analyze Loop gain stability under different conditions.

a Phase detector has a transfer function of k/s, like an integrator, since the integral of frequency is phase and the output , k will be in terms of volts per cycle of phase error. Thus k is usually the mixer voltage with a scale factor of 1/2 or 1 depending on the mixer range.
Mixers that integrate by opening the output with pump up or down use an open circuit and integrate voltage by pumping current according to the phase error, like an integrate and hold circuit.

Click to expand...

Hi.. Sunny

thanks for your point... you mentioned about k/s what does it mean?

and k =1 or 1/2 what do you mention by this..?
and mixer means charge pump or other circuit..

please explain clearly..

thanks..

- - - Updated - - -

dick_freebird said:

The gain near threshold of the logic gate, with the supply
voltage, determines the width of the linear input region.
This, with signal risetimes, then determines the maximum
jitter time that can be added / subtracted by noise voltage
superimposed on the input (or supplies). So the gain is not
inconsequential. It may not be a prime target for analysis
as the outcome of interest is the rollup gate switching
behavior, gain and risetimes / bandwidth.

Click to expand...

Hi dick_freebird..
thanks for the point..

so near the threshold region .. due to some random noise we get jitter and phase noise..am i right?
you mentioned about width of linear input region... how this gain affect input region width..?

thanks..

Strictly spoken, the term PFD (phase and frequency detector) implies a digital ("type II") circuit, because a mixer would act as a phase detector only. In so far I presume, we are talking about an input voltage independent "gain" respecticvely k/s value.

K is a linear constant of gain
s is a mathematical term for modulation or difference frequency ( s=jῳ )

Here is a teaching course presentation https://users.ece.gatech.edu/pallen/Academic/ECE_6440/Summer_2003/L090-PLLEqs&MeasA(2UP).pdf

Hi sunnyskyguy..

thanks for the notes.. though they are mathematical oriented..i found some interesting points..

so the gain depends on PFD chargepump and loop filter..

the PFD makes the up and down errors with respect to the frequency and phase errors..
so it contributes to the gain of the charge pump and filter..

is that right?

thanks

yes
Negative Feedback controls the error. Just as in any PID Control Loop, (Proportional, Integrator, Derivative) a PLL can have similar properties depending on Mixer and filter type. The tradeoffs are lock time, jitter, capture range are not easy to model but Bode Plot helps in understanding.

SunnySkyguy said:

yes
Negative Feedback controls the error. Just as in any PID Control Loop, (Proportional, Integrator, Derivative) a PLL can have similar properties depending on Mixer and filter type. The tradeoffs are lock time, jitter, capture range are not easy to model but Bode Plot helps in understanding.

Click to expand...

hi sunny
thanks for the info... and i have a doubt..
PFD(MIXER) --> is there more configurations for PFD design.. since it just creates up an down pulses.. and more or less it is a digital circuit..

so it solely depends on loop filter.. am i right?
and on which basis... loop filter should be selected?
can you please explain or refer something..
thanks.

There are dozens of different implementations of mixers for PLL's I once used a sample and hold mixer sampling a sawtooth with edges of a data pulse that could have as few transitions as 1 in 128 bits NRZ so the clock had to very stable and accurate. but the signal to noise ratio was good.

hi. sunny..
it is good..

now i have to compare reference squre wave with the feedback squre wave...
so i think.. the PFD configuration doesn't play a bigger part than loop filter..

because it fully depends on charge pump and loop filter which feeds the VCO..

is my statement correct?
thanks

Yes your response and jitter is controlled by the loop filter. Usually fixed gain of 2 to 5 and HF gain of 10 to 20 does the trick.