Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Gain characterization of a simple voltage amplifier

Status
Not open for further replies.

elessareldarion

Newbie level 1
Newbie level 1
Joined
Feb 26, 2010
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
Lund, Sweden
Activity points
1,291
I'm simulating the time response of a voltage amplifier, which only consists of a single MOSFET. The circuit diagram is attached below.

I want to extract the voltage gain from this amplifier and I am wondering how large the load impedance should be? What is the normal conditions in which one tests the gain? I am thinking that maybe the load impedance should be infinitely large or matched to the circuit output impedance in some way.

Also, when performing this kind of study, how large should the amplitude of the input signal be? I mean, the larger the input amplitude, the higher the distortion on the output signal. This is due to the non-linear behaviour of the FET.

What other figures of merit, other than gain, could be used to charcterize this amplifier?
 

Quote:I want to extract the voltage gain from this amplifier and I am wondering how large the load impedance should be? What is the normal conditions in which one tests the gain? I am thinking that maybe the load impedance should be infinitely large or matched to the circuit output impedance in some way.

There are no "normal conditions" for loads during testing the gain of a transistor stage. As each transistor has a high output impedance (and acts more or less as a current source) the "effective" resistor combination connected with the output node determines the gain (remember: gain=transconductance*resistor). This "effective" resistor always is Rd in parallel with the load RL.
By the way: This is the reason to use buffer stages if you want to connect two stages in series which should not influence each other.

Quote: Also, when performing this kind of study, how large should the amplitude of the input signal be? I mean, the larger the input amplitude, the higher the distortion on the output signal. This is due to the non-linear behaviour of the FET.

Simple answer: As low as possible !
As the gain is a small signal (linear) parameter the influence of non-linearities of the circuit should be kept as small as possible!
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top