fx2lp virtual comport, manual commit problem

void TD_Init(void)             // Called once at startup
{
	// Return FIFO setings back to default just in case previous firmware messed with them.
	SYNCDELAY; PINFLAGSAB   = 0x00;
	SYNCDELAY; PINFLAGSCD   = 0x00;
	SYNCDELAY; FIFOPINPOLAR = 0x00;
	
	// Global settings
	SYNCDELAY; REVCTL = 0x03;
	SYNCDELAY; CPUCS  = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1);  // 48MHz
	
	// IFCLKSRC 3048MHZ IFCLKOE IFCLKPOL  ASYNC GSTATE IFCFG1 IFCFG0
	SYNCDELAY; IFCONFIG = 0xE3; //1110 0011 
	
	// EP1OUT & EP1IN
	SYNCDELAY; EP1OUTCFG = 0x00;
	SYNCDELAY; EP1INCFG  = 0xA0;
	
	// VALID DIR TYPE1 TYPE0 SIZE 0 BUF1 BUF0
	SYNCDELAY; EP2CFG = 0xA2;
	SYNCDELAY; EP4CFG = 0xE2;
	SYNCDELAY; EP6CFG = 0xD0;//1101 0000
	SYNCDELAY; EP8CFG = 0x00;
	
	// 0 INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN 0 WORDWIDE
	SYNCDELAY; EP2FIFOCFG = 0x00;
	// SYNCDELAY; EP2FIFOCFG = 0x10;
	SYNCDELAY; EP4FIFOCFG = 0x0C;
	SYNCDELAY; EP6FIFOCFG = 0x0C;
	SYNCDELAY; EP8FIFOCFG = 0x00;
	
	SYNCDELAY; EP4AUTOINLENH = 0x02;
	SYNCDELAY; EP4AUTOINLENL = 0x00;
	SYNCDELAY; EP6AUTOINLENH = 0x02;
	SYNCDELAY; EP6AUTOINLENL = 0x00;
	
	SYNCDELAY; FIFORESET = 0x80;
	SYNCDELAY; FIFORESET = 0x82;
	SYNCDELAY; FIFORESET = 0x84;
	SYNCDELAY; FIFORESET = 0x86;
	SYNCDELAY; FIFORESET = 0x00;
	
	SYNCDELAY; OUTPKTEND = 0x82;  
	SYNCDELAY; OUTPKTEND = 0x82;
 
}
 
void TD_Poll(void)             // Called repeatedly while the device is idle
{
 
if( !( EP2468STAT & 0x01 ) )
{ // EP2EF=0 when FIFO NOT empty, host sent packet
	OUTPKTEND = 0x02; // SKIP=0, pass buffer on to master 
}
 
if (!(EP1INCS & 0x02))      // check if EP1IN is available
  {
	EP1INBUF[0] = 0x0A;       // if it is available, then fill the first 10 bytes of the buffer with 
	EP1INBUF[1] = 0x20;       // appropriate data. 
	EP1INBUF[2] = 0x00;
	EP1INBUF[3] = 0x00;
	EP1INBUF[4] = 0x00;
	EP1INBUF[5] = 0x00;
	EP1INBUF[6] = 0x00;
	EP1INBUF[7] = 0x02;
	EP1INBUF[8] = 0x00;
	EP1INBUF[9] = 0x00;
	EP1INBC = 10;            // manually commit once the buffer is filled
  }
}