architecture rtl of my_entity is
signal Address_signal: std_ulogic_vector(15 downto 0);
signal Data_signal: std_ulogic_vector(15 downto 0);
signal Write_signal: std_ulogic;
signal Ready_signal: std_ulogic;
signal Clock: std_ulogic;
-- Note: The procedure 'Write' could also be defined here. However,
-- if you did this, then you would also have to list all of the
-- signals that are used within the procedure as ports to the
-- procedure. Many times though only a single process needs to
-- drive these signals so the procedure can be defined within the
-- scope of the process in which case those signals can be assigned
-- or used without having them listed on the interface to that
-- procedure as will be demonstrated below.
begin
process Main is
procedure Write(Addr, Data: std_ulogic_vector) is
begin
Address_signal <= Addr;
Data_signal <= Data;
Write_signal <= '1';
wait until (Ready_signal = '1') and rising_edge(Clock);
Write_signal <= '0';
end procedure Write;
begin
Write(x"1234", x"5678"); -- Write '5678' to address '1234'
....
end process Main;
end rtl;