Functions and subprograms

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There is no such thing as a program in VHDL, so there is no such thing as a subprogram.
 

**broken link removed** 2.9 Subprograms
**broken link removed**
 
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both functions and procedures are synthesizable. At least, as long as the code within them is synthesizable.

procedures are often used for simulations, while functions are fairly common. You should do a test run with any complex function to see how it synthesizes. The tools don't always pick up an optimal solution.
 

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