mouhamedmb
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Hello,
I have the following errors in test file of my project ,first when when launching the C simulation I have a problems:
second when I open the file test reports these errors.
multiple markers at this line
-Function 'testph' could not be resolved;
-symbol 'testph'could not be resolved;
#
I have the following errors in test file of my project ,first when when launching the C simulation I have a problems:
Code:
INFO: [SIM 2] *************** CSIM start ***************
WARNING: [SIM 51] HLS only supports CLANG compiler in Linux.
INFO: [SIM 4] CSIM will launch GCC as the compiler.
Compiling ../../../../codegen/lib/testtestphase/examples/main.cpp in debug mode
../../../../codegen/lib/testtestphase/examples/main.cpp:33:26: fatal error: rt_nonfinite.h: No such file or directory
compilation terminated.
make: *** [obj/main.o] Error 1
CRITICAL WARNING: [SIM 100] 'csim_design' failed: compilation error(s).
INFO: [SIM 3] *************** CSIM finish ***************
second when I open the file test reports these errors.
multiple markers at this line
-Function 'testph' could not be resolved;
-symbol 'testph'could not be resolved;
#
Code C - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 define MCR_SIZE 60 void testtestphase (AXI_VAL in_stream[MCR_SIZE], AXI_VAL out_stream[3*MCR_SIZE], volatile ap_uint<1> *hw_trig) { // Map ports to Vivado HLS interfaces #pragma HLS INTERFACE ap_fifo port=in_stream #pragma HLS INTERFACE ap_fifo port=out_stream // Map HLS ports to AXI interfaces #pragma HLS RESOURCE variable=in_stream core=AXIS metadata="-bus_bundle INPUT_STREAM" #pragma HLS RESOURCE variable=out_stream core=AXIS metadata="-bus_bundle OUTPUT_STREAM" #pragma HLS RESOURCE variable=return core=AXI4LiteS metadata="-bus_bundle CONTROL_BUS" #pragma HLS INTERFACE ap_none register port=hw_trig dut_testtestphase <float, 60, 1*60, 4, 5, 5>(in_stream, out_stream, hw_trig); return; }
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