Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi ,
After tapeout the chip will be tested for Functional patterns ( for the functionality of chip ) & Test patterns ( the ATPG test patterns which checks for defects in the chip by the DFT logic added in the design in Test mode) .
All these are checked in the Tester level were the chip will be hand-off.
i dont think it is necessary. Becaue the clock frequency is lower than that in real working. it cant check the timing.
My opinion is we only need ATPG, we can ingore the function test pattern.
Hi ,
Now a days all the ASIC's come with internal PLL .So the Source of the PLL will be considered based on the Maximum frequency of the Tester ( say 100 Mhz ) .From 100 Mhz using PLL multiplers / dividers we can arrive at the functional frequency .All these things will be decided at the start of Chip design phase considering all aspects/limitations of the Tester .This is one mode of Functional pattern testing & also the same can be tested functionally bypassing the PLL at less frequency to just ensure the ASIC works fine at low frequency incase the PLL have problem.
Now the quesyion is how u arrive at the functional patterns , we can conver the vcd dump to stil ,wgl testfor.mat and the tester guys will be able to test functionally.
Also the ATPG test patterns will be tested as well .Apart from this the MEMORY , IO cells . PAD will aslo be tested .
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
