Fully differential VCO ring oscillator problem with MOSFET load

[Junus2012]

Dear friends,

I have designed an odd number fully differential VCO as shown below

the differential cell is given below (with the transistor sizes)

I used replica biasing circuit with feedback loop to bias the delay cells as given below

The loop gain of the op-amp is very large so that I have guaranteed that output voltage is equal to the vctrl (some people call it vref), as exactly explained in literature. However, literature staes that the biased NMOS load of the delay cell are in the triode region, but in my case it is in saturation region. I have tried to change the vctrl to many values but still the load is showing me in saturation.
to confirm the loop functionality, I have sweeped the biasing current in wide range and also by varying the supply voltage, the loop was strong enough to keep to keep the output swing equal to vctrl..
I did another DC simulation to test the steady state circuit of the circuit by applying DC input to the cell and breaking the VCO feedback, looks every cell is working fine like a perfect inverter.

my trouble come with transient simulation, the circuit is not at all oscillating. At the start I thought it is about the intial condition of the simulator but I then used to set the initial condition from the simulation convergence aid, again not working.

the last step in my investigation I replaced the NMOS load transistors with an equivalent equal normal resistors (exctracted from vctrl/actual current), the circuit start to oscillate but with not equal outputs,

I do appreciate your help to solve my problem with the NMOS load,
do you think I have transistors size issue?

Thank you in advance
Regards

 

[sutapanaki]

If I understand correctly your circuit, you are trying to regulate the output to Vctrl by this replica. But if the ring oscillator finds an operating point where it is happy staying without oscillating, that's what it will do. However, it can be as simple as just kicking the oscillator forcing it into oscillations. Did you do that? For example, inject a short current pulse differentially somewhere in the ring oscillator loop and let it alone after that and see if it will start oscillating and continue oscillating.

By the way, I have read before a patent, that's not quite the same but similar to the things you are trying to do.

https://patentimages.storage.googleapis.com/6e/4a/a1/47e1f92fad530c/US7126431.pdf

 

[Junus2012]

Thank you Suta for your reply

indeed I have tried to inject pulse voltage on the VCO loop differential but not worked,
As I told I have set the intial condition of the nodes manually from Cadence
you can try that if you go to "Simulation">"Convergence Aid">"Intial Condition".

Also I have changed this NMOS load with an equivalent resistor and was working,
I am thinking that I have a problem with this PMOS load or my circuit sizing

and thank you for sharing me this patent

 

[Junus2012]

I have somehow solved the problem of the oscillator but still has minor effect,
I have connected even number of stages as delay buffer chain and I made the inversion only occurs one time between the final stage to the input, if you look to former post the circuit was inverting on every delay stage, dont know why this solved the problem but I think the individual cells now have relaxed operation

The minor problem is that my output is not following the control voltage, I put voltages between 1.25 to 2 V but he stuck around 800mV as you below

The amplitude for me is not a problem cause I could corrected the output level using inverters, but what matter me is that I have lost the control of this voltage, which I was thinking to use to tune the circuit against PVT.
could be the amplifier GBW one of the reasons? I am using an opamp with GBW = 2MHz and the oscillating frequency is about 9 MHz.
Thanks

 

[sutapanaki]

From your simulation what is vctrl and vrbias and what is the difference between the inputs of the opamp?

 

[Junus2012]

Dear Suta,

I have solved the issues of oscillation, the NMOS load transistors must be long enough to be in triode region,

Remaining for me new question, if you go back to post 1, what are the GBW requirement of the opamp?
thank you

 

[sutapanaki]

Since you are working on a replica, it looks to me that you don't have to have a lot of GBW. Maybe just enough to settle any variations on vrbias to an acceptable level. Or, it can well turn out that your GBW will be simly defined by the amount of the DC loop gain you have and the dominant pole of the loop, because you need to maintain sufficient phase margin.