fully differential telescopic cascoded compensation OTA

[pra]

fully diifferential mos ota

Hi,
I am designing a fully differential OTA. with out CMFB i designed the telescopic OTA
with dc bias conditions. Then i designed a SC CMFB circuit.
I want to measure the openloop gain in dB's but i am getting -ve result.
can anybody please help how to design this? Is it able to measure the open loop gain with out using SC CMFB?
TIA
pra

 

[terryssw]

fully differential telescope opamp compensation

Measuring DC open loop gain usually use AC analysis, which cannot use in SC CMFB circuits since SC-CMFB has only the effect in transient events. For simulate the open loop gain, you can use some type of ideal common-mode feedback.

 

[pra]

fully differential telesopic biasing

Hi Terryssw,
Thank you for ur help.
I am getting small dbts.
i am attaching my OTA design with out CMFB circuit
first i done the dc bias simulation by giving some voltage at i/p differential pair and make all the transistors in saturation region.
then i connected a ac source as shown in the figure for caluclating tha gain and phase margin but i am getting very low gain and peculiar phase o/p.
is dc bias reqd for the i/p in ac simulation!!!!
i m sure that my design has more gain but i am getting a gain of 15db
is there any fault in simulating it!!!
all these simulations are done without using CMFB circuit
i m using tanner spice for simulation
please help me regarding this.

sorry for my poor english
thank you

 

[srivatsan]

fully differential compensation

Well, I think I had this problem, a while before (I usually document all of my previous mistakes). But it was one of my silliest mistakes in my life. The output I got showed me around 30dB, when I designed for 80dB. Well, my "output" itself was misinterpreted. I had only my output value and not the input value. SO the Gain is actually Vout (in dB) minus Vin (in dB). I find no problem in your circuit. I think it is the interpretation of your output plot which I think is the problem.
So why dont you post the output plot.. it could be useful..... I could be wrong too....

I hope it helps.

- srivats

 

[pra]

Hi Srivatsan,
I am attaching my o/p plots with this.
according to u, i had given the i/p of 1v magnitude so the vin is 0db
i m getting the o/p of 25db max. and the phase o/p is entirely different and i m not able to understand what the problem is!! can u please explain what the mistake might be!
Thanks
Pra

 

[terryssw]

There would be many potentials to cause such problems. I have figure out two of them:

1. What is your channel length for all transistors? Your current in the two output legs? what's your input transistor transconductance gm? What's your expected gain value (i.e. through your calculations)? I am asking this because suppose, if you choose quite small channel lengths (e.g. L < 0.35 um) then it is quite possible you get a gain as low as 20 dB although you use cascode structure.

2. What's your output DC biasing voltage? Personally I don't suggest to simulate the gain without the use of any CMFB circuit, but you can still do it by fine tuning your input DC biasing voltage to get your output voltage around the middle of supply rail. Check this to ensure that your output DC bias is in the middle of VDD. Finally, yes, you are right, you must setup input DC bias in order to do AC simulations. Also pls really ensure that all transistors in saturations.

 

[srivatsan]

First of all, I notice in your frequency response - a peaking response. It would lead to instability. Forget about correct gain value. Try to eliminate that peaking.

Second: Check whether all the transistors are in saturation. How to identify it? Well, apply only the DC voltage(s) and check the voltages at all the nodes and you know the condition for checking whether the transistors are in saturation. Note that for short-channel, it is slightly difficult, or rather little time-consuming. Then check whether you have appropriate current in the bias transistor, and both the input transistor. Once you know those details, check the same for 0.5v above and below that DC value. then set the AC signal for 1/100000v and do the AC analysis.

the foregoing points may help.

Post the W/L for the circuit, anyways. It may help.

- srivats

 

[pra]

Hi Terryssvw & Srivatsan
Thank You for ur support and suggestions

I taken care of making all transistors in saturation.
But i am not sure whether they are in saturation for different i/p bias volages. I will check those ones now.
I changed the CL values to reduce the peak in the gain, but I am not able to reduce it. Is there any other ways to make the circuit stable!!
I had designed for 10000 open loop gain.
My transistor W/L values are : i/p diff transistors(M1,2) : 212.8u/1.4u
cascode Nmos(M3,4): 478u/0.35u
o/p pmos(M5,6): 160u/0.35u
Pmos current source(M7,8):102u/1.4u
Nmos tail (M9):1020u/0.35u
biases are vb9=0.76275
vb1=1.04; vb3=1.425 ; vb5=1.14 ; vb7=1.333119 ;

If there is any mistake in my design then please let me know.
Thank you
Pra

 

[terryssw]

From the transistor sizing, it seems you should have no problem to have your opamp gain > 60 dB. Just really make sure all transistors are in saturation and the output of the voltage is arround the middle of the supply.

 

[pra]

Hi Terryssw,

I had checked that all transistors are in saturation for a given input dc voltage and the o/p voltage is at middle of the supply. From Mr.Sirvatsan, when i changed the input dc voltage the transitor region of operation is changing.

initially i found out the bias voltages manually from my assumptions and verified it in spice. To make all the transistors in saturation region i changed the bias of the top PMOS transistor. I fixed the bias to those transistors when all the transistors are in saturation region. after this if i changed the i/p dc voltage then all transistors are not operating in saturation region. I am thinking that I am doing wrong method while fixing the bias voltages. Please tell me the correct procedure to fix the bias voltages..

Thank you
Pra

 

[jiangwp]

I think there are some factor affecting your simulation. Such as:
1.Be sure the differential output common level to be the same when you do ac simulation . In the meantime , the telescope legs transistors are all in saturate.
2.The SC CMFB is driven by the samll signal transfer. Or you need the Specture RF simulator of Cadence for SC ac simulation.
3.Before you do ac simulalion , Be sure the operation point is correct.

I think you can do ac simlulation with CMFB and Close loop of the OPAMP.
Then the gain will be increased.

 

[pra]

I am using tanner tools for spice simulation.
I am getting some basic doubts.
please clarify them.
1) to measure the dc analysis we give some bias voltage to the input of the transistors so that all MOS's are in saturation. when we want to check the ac analysis is the dc voltage is required??? if required then it is for both the i/p MOS's are just as i connect in the circuit as shown in my message!!!!
if not required how will the opamp works for those voltages!!!!!!!
if the bias voltage is required then that shud be generated by biasing ckt!!!!!
2) how will we measure slew rate for a fully differential op-amp!!!!
3) if I sweep the i/p voltage of the +ve i/p and given bias voltage to the -ve i/p then we get inverter charecterstics at the VO+ and what abt the o/p at VO-!!!!!

can anybody tell me where can I find the different tests that can be done to a fully differential amplifier and how?

thank you

 

[jasonhu]

hi Pra,

The DC bias voltage are always needes in any simulations. by sweeping the bias
voltage you can get the appropriate value and then generate them through bias circuits and current mirror.
the slew rate can be computed by the whole current and the capacitor at the this leg and output node, also it can be validatede by tools.

anyway ,google "EE240" may help u .[/quote]