I'd'like to design a simple fully differential OTA for a switched capacitor integrator. As it needs to be very low power, I'm wondering how to start the design and how to fixe the W and L of the transistors? The design I made doen't have the common mode in the middle range (Vdd/2).
I read some papers about the Gm/ID methodology, but as the best case is in moderate inversion, I'm wondering how to achieve this requirements. What is a typical procedure to design an OpAmp?
Can anyone help me how to start a design?
Sure, it's a very good way to start and complete a design, IMHO.... regarding to the gm/ID methodology. I don't know if it's the best way to start a design
I'm wondering how could I simulate the VA voltage? I've the gm/Id vs Vgs curve (dId/dVgs/Id) ) and the ro curve (dVds/dId) but for the early voltage, I only can compute it by hand calculation. Any idea how to have this data and if it's a good way to start?
Félicitations!I got the VA vs Vds curve from your thread! I calculated it by hand and I got the same results!
It should be possible with the help of ADE's calculator tool. See the last sentence in my posting!... is there a way to plot gm/ID vs VA ?
You are quite right, but we used it only as buffer (for reference voltages).I have a feeling this circuit will have an ill-defined quiescent current in its output stage. At balance and driving no load, the first stage amplifier should have an output voltage of Vgs commensurate with the second stage's Q-current equaling the first stage's. The NMOS and PMOS input stages will have different offset voltages, and since they are forced to have equal input voltages it will manifest as an output voltage offset (since their currents aren't summed but are instead independently converted to voltage); rather than Vgs, each output will be Vgs±Voffset*gm*ro (plugging in appropriately adjusted values for Voffset and ro).
Right again! MC sims showed huge output stage current variations:Depending on the offset magnitude and the value of ro, this could cause some serious quiescent current variations (i.e., the output stage's Q-current could be zero, or it could be tens of µA) and possibly prevent operation altogether.
I would think this should show up in Monte Carlo sims. Has this circuit been built in silicon?
Not really, but good enough for our purposes:Not to mention, it doesn't appear like it should work well with rail-to-rail inputs.
It should be possible with the help of ADE's calculator tool. See the last sentence in my posting!
It should be possible with the help of ADE's calculator tool. See the last sentence in my posting!
They look reasonable. And they match with your above gm/Id and VA vs. sweep-time curves.Do these curves look good or not? Just wondering if I made a calculation mistake.
Not necessarily: For high bandwidth you just need large gm, for which you need high Id values. And this is better achieved (means: area and parasitic cap saving) by large gm/Id causing low VA values. Actually high frequency amplifiers tend to use small transistor lengths.For high L, we can have a high bandwidth.
Depends on quite a lot of your priority requirements: high UGF vs. low power, transistor matching (offset) vs. area consumption, (low) noise ...And the higher gm/ID, the best efficiency. So if I understand, the best thing is to use a huge gm/Id, but in this case VA will be small and the ro. What is the strategy to adopt once we got these curves?
I do not care about the area consumption, priority is low power, the GBW could be tens of kHz (Switched capacitors at 32kHz) and a gain of 100 could be good enough.
... the CMRR must be low (as low as possible, so maching is important).
This curves have been simulated with W=2µm.
So for starting, you suggest to design a simple differential amplifier and current mirror for biasing and test with different Ids?
Sure: from this curve you get the W/L ratios.... but what about the W? Some papers suggest to plot gm/ID vs ID/W/L
Via the necessary DC gain you get VA and then an upper limit for the gm/Id value from this curve, considering Lwhat's the difference btw gm/ID vs VA?
So use a large enough L for the input transistors (in order to get a good layout matching, you could interdigitate them, or split them into an array).I think the design depends on the offset at the inputs. Of course, we can't have a few mV at the gates of the inputs transistors
It shouldn't, as you probably will have a large feedback ratio (Av[open loop] / Av[closed loop]).... and does the gain or the overall performances depends on the inputs voltages?
Now what else do you need?I still didn't understand how to size the transistors
No, I don't think they are wrong, even if I had estimated a factor of 10 lower for the Id/(W/L) value (i.e. x 10-6 at the end of the abscissa) for the 90nm process. Pls. check once more!Are these plots wrong?
Now, the other way round: you should choose a larger gm/ID value, more in weak inversion, which gives you even better transconductance (gm) efficiency, but will decrease your DC gain because of lower VA (and your UGB).Or may be I should choose a different gm/ID value, in moderate or strong inversion?
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