full subtractor using case statement...plzz tell me error

[rids1]

module full_sub(a,a1,c,d,b,e);
input a,a1,c;
output reg d,b,e;

always@(a1 or a or c)
begin
e={a,b,c};

case(e)
000:
begin
d=0;
b=0;
end

001:
begin
d=1;
b=1;
end

010:
begin
d=1;
b=1;
end

011:
begin
d=0;
b=0;
end


100:
begin
d=1;
b=0;
end

101:
begin
d=0;
b=0;
end

110:
begin
d=0;
b=0;
end

111:
begin
d=1;
b=1;
end
endcase
end

endmodule

 

[zel]

a lot of latches.

 

[rids1]

plz tell me hw i can correct it........

 

[nikhilna007]

is it e={a,b,c}; or
e={a,a1,c};


also 'e' is declared as one bit, but e={a,b,c} is three bit
so the tool will truncate the three bit into one bit.

so case expression never matches..