Full Custom Design Testing Issue

[philewar]

Hello Gurus,

You know that cell-based design employs a scan-chain method to perform DFT. When your chip goes mass production, test vectors are feed into the chip, walk through the scan-chain, and tell you whether the chip works or not.

The question is for full custom layout design. How to tell your component, e.g. domino circuit, barrel-shifter, are working well via a way simillar to scan-chain plus ATPG? Or What is the way industry using now?

Thx in advance.


Best,

philewar

 

[gerryhsu]

Mentor DFTAdvisor, FastScan, ATPG and the same counterpart Synopsys tools do the job. Consult your vendor of choice document for more info. It's too long to mention here

 

[philewar]

Thank you for your input.

But my question is how to do DFT when you do full custom, i.e. you draw your layout, such as dynamic circuits barrel-shifter. You know, fastest alu are all full custom.

Best,

philewar

 

[gerryhsu]

Thank you for your input.

But my question is how to do DFT when you do full custom, i.e. you draw your layout, such as dynamic circuits barrel-shifter. You know, fastest alu are all full custom.

Best,

philewar

Yes, You design the normal circuitry. Do simulation. Implement DFT technique (Using Scan FF instead of regular FF). Do simulation again. Check if the performance is acceptable. Then do full custom layout with the DFTed circuitry.

 

[eternal_nan]

As far as I know full-custom macros can be production tested in one
of the following three ways:
1. Built In Self Test (BIST)
You have an input on the macro that when appled causes the macro
to run a self-test and report pass/fail (1/0) on an output pin.
2. Scan built into the macro
Usually you need to set away separate SI/SO chip pins just for the
macro in order to avoid timing problems stiching the macro's scan
chain with outside scan chains. However this is not absolutely neccess-
-ary as you can use lock-up latches to interface to the macro's scan
chain.
3. Functional Test. At this point I think functional test is the most often
used method, basically you run a simulation that excercises the macro
and capture all chip input/output values to run and compare on the
tester.

Hope that helps.