full adder code in vhdl programming

[sumati]

I want a full adder programming code in vhdl.How can I get software for vhdl programming.How can i get licence for it. Any HELP plz!!!

 

[medra]

you could download xilinx webpack ( free license) , you will also found a lot of codes in the templates including adders.

 

[mindthomas]

You can download the Xilinx Webpack for free here: Xilinx: Downloads

A fulladder VHDL code looks like this:

-- This is just to make a reference to some common things needed.
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- We declare the 1-bit adder with the inputs and outputs
-- shown inside the port().
-- This will add two bits together(x,y), with a carry in(cin) and
-- output the sum(sum) and a carry out(cout).
entity BIT_ADDER is
port( a, b, cin : in STD_LOGIC;
sum, cout : out STD_LOGIC );
end BIT_ADDER;

-- This describes the functionality of the 1-BIT adder.
architecture BHV of BIT_ADDER is
begin

-- Calculate the sum of the 1-BIT adder.
sum <= (not a and not b and cin) or
(not a and b and not cin) or
(a and not b and not cin) or
(a and b and cin);

-- Calculates the carry out of the 1-BIT adder.
cout <= (not a and b and cin) or
(a and not b and cin) or
(a and b and not cin) or
(a and b and cin);
end BHV;

 

[atemnik]

You can download the Xilinx Webpack for free here: Xilinx: Downloads

A fulladder VHDL code looks like this:

LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-----------------------------------------------------------------
entity fulladder is
port( a, b, cin : in STD_LOGIC;
sum, cout : out STD_LOGIC );
end fulladder;
-----------------------------------------------------------------
architecture Behavioral of fulladder is
signal s1,s2,s3: STD_ULOGIC;
constant gate_delay: Time :=100 ps;
begin
s1<=(a xor b) after gate_delay;
s2<=(cin and s1) after gate_delay;
s3<=(a and b) after gate_delay;
sum<=(s1 xor cin) after gate_delay;
cout<=(s2 or s3) after gate_delay;

end Behavioral;

 

[mindthomas]

LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-----------------------------------------------------------------
entity fulladder is
port( a, b, cin : in STD_LOGIC;
sum, cout : out STD_LOGIC );
end fulladder;
-----------------------------------------------------------------
architecture Behavioral of fulladder is
signal s1,s2,s3: STD_ULOGIC;
constant gate_delay: Time :=100 ps;
begin
s1<=(a xor b) after gate_delay;
s2<=(cin and s1) after gate_delay;
s3<=(a and b) after gate_delay;
sum<=(s1 xor cin) after gate_delay;
cout<=(s2 or s3) after gate_delay;

end Behavioral;

Wow, hold on! Why are you using all those "after" statements?
You can't use "after ...." in real VHDL development for implementation in your FPGA or CPLD. There is no "logic" to make an "after..." statement.
The after statements are used in your test bench for simulation your logic!

Also I am not sure if your code is alright. Instead I would recommend you to use this code:

library ieee;
use ieee.std_logic_1164.all;

entity fullAdder is
    Port(
        a    : in std_logic;
        b    : in std_logic;
        cin  : in std_logic;
        s    : out std_logic;
        cout : out std_logic);
end fullAdder;

architecture arch of fullAdder is
    signal aXorB : std_logic;
begin
    aXorB <= a xor b;
    s     <= aXorB xor cin;
    cout  <= (a and b) or (cin and aXorB);
end arch;

Borrowed from **broken link removed** which has a good explanation too.

 

[atemnik]

Right... Did you compile your "code" for "real VHDL development" ? LOL

 

[mindthomas]

Right... Did you compile your "code" for "real VHDL development" ? LOL

No, I haven't tried synthesizing this one - though it should work as it makes the right logic for the full adder circuitry.

 

[atemnik]

in arch... don't forget to declare that 's' and 'cout' of yours.

 

[mindthomas]

in arch... don't forget to declare that 's' and 'cout' of yours.

Nope, not neccesary! It is declared in the entity port setup...

 

[TrickyDicky]

in arch... don't forget to declare that 's' and 'cout' of yours.

He did already.

 

[xtcx]

Wow, hold on! Why are you using all those "after" statements?
You can't use "after ...." in real VHDL development for implementation in your FPGA or CPLD. There is no "logic" to make an "after..." statement.
The after statements are used in your test bench for simulation your logic!

Also I am not sure if your code is alright. Instead I would recommend you to use this code:

library ieee;
use ieee.std_logic_1164.all;

entity fullAdder is
    Port(
        a    : in std_logic;
        b    : in std_logic;
        cin  : in std_logic;
        s    : out std_logic;
        cout : out std_logic);
end fullAdder;

architecture arch of fullAdder is
    signal aXorB : std_logic;
begin
    aXorB <= a xor b;
    s     <= aXorB xor cin;
    cout  <= (a and b) or (cin and aXorB);
end arch;

Borrowed from **broken link removed** which has a good explanation too.

Well, what Atemnik has given is a good simulation model of a full adder, but other than that it still looks good. I dont think both codes (the one from Mindthomas) will generate a different hardware when synthezised. however Mindthomas code looks clean

 

[atemnik]

Well, what Atemnik has given is a good simulation model of a full adder, but other than that it still looks good. I dont think both codes (the one from Mindthomas) will generate a different hardware when synthezised. however Mindthomas code looks clean

Can you compile your code and post a screenshot? Thanks.

 

[mindthomas]

Can you compile your code and post a screenshot? Thanks.

Ok, here you go.
**broken link removed**