ft simulation in Cadence Spectre

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dfrndez

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cadence + unit current gain frequency

Hello,

I had a basic question about simulating the short circuit unity gain frequency of a mosfet.

Attached you can see the simple schematic. I have supplied a dc voltage bias of .9 volts, and an input current source with an ac magnitude of 1 and a dc current of 0.

When I run the simulation (ac) the output ac current is 0, what am I missing? Since this is a mosfet, I don't think I need a dc current bias at the gate. Do the two voltage sources (one the bias and one the supply) need to have an ac magnitude specified?

Any insight would be appreciated.

thanks
 

ft simulation

dfrndez said:
Hello,
.............................
I have supplied a dc voltage bias of .9 volts, and an input current source with an ac magnitude of 1 and a dc current of 0.
Click to expand...

Do you really try to excite the FET with an ac CURRENT ?
A FET is a voltage controlled device ! Try an ac voltage.
 

cadence mos ft


Actually there's no problem in stimulating the FET with an AC current source because the device has a parasitic cap at its input, generating an effective AC voltage; so theoretically this approach could work. Now, using a DC current source to bias the circuit WON'T work, because the effective voltage at the input would grow linearly with a constant current value, generating a simulation error (fortunately, this is not the case for this circuit).

The problem with this circuit in particular is that the DC bias voltage is in PARALLEL with the AC current source, so when the software does the AC analysis the DC voltage source is treated as a short circuit, which means that the FET's gate is shunted to ground (all the current is going directly to ground).

So, if you are planning to use an AC voltage source or an AC current source remember to connect your bias voltage in series with it.

Hope this helps,

diemilio
 
ft simulation of mosfet


OK, I agree - it could work as long as there is a parasitic cap in the MOSFET model directly between the gate terminal and the source terminal. But I think in several cases this cap is connected between some kind of internal source node - excluding a resistive part between this node and the external terminal.
Nevertheless, for my opinion it is "exotic" to use an ac current source in conjunction with a parasitic capacitance rather than a voltage.
 

cadence + ft simulation


I agree with you, it's not very common

I just wanted to emphasize that the error is the parallel connection of the DC voltage source.

regards,

diemilio
 

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    dfrndez

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transit frequencey cadence parameter

Thanks for the insight. You are correct, the voltage source actually should have been in series. There was another issue in that the software when running a DC operating point analysis essentially set the gate to 0 V, regardless. I used a convergence aid to set the gate node to a fixed bias.

However when you look at the output ac current versus the input ac current, the current gain is constant across frequency which is not correct. I'm not sure what to make of that.

I'm ultimately designing an LNA, the idea of this particular circuit is just to determine ft, so as to approximate degeneration inductance, and other parameters in that LNA circuit.
 

simulation of short circuit current in cadence

I just realized that f you connected your AC current source in series with a DC voltage source for the "bias point calculation" the simulator will model the AC source as an open circuit, so your gate will be "floating". I think that's why your having the bias problem. I suggest that you follow LvW's approach and use a DC voltage source in series with an AC voltage source (or just use one source in which you specify both the AC and DC voltages).

Know, if you want to keep using the AC current source as your input you will have to come up with a decouple DC bias circuit, but then, this will affect your results.

hope this helps,

diemilio
 

measure ft cadence

Thanks. The ac voltage approach is a bit unclear because I am looking for current gain. You could get ioutput/vgs and then divide the result by (Cgs+Cgd), not exactly sure how exact that approach especially over a large frequency range. I may end up doing this or perhaps just simulating gm, and Cgs and then approximating ft as gm/cgs.

I looked online recently and saw the following schematic used to simulate ft which is interesting though that would too appear to have a biasing issue :

https://www.cadence.com/Community/blogs/rf/archive/2008/08/09/simulating-mos-transistor-ft.aspx
 

how to simulate ft

It is correct to use a voltage source to dc bias the gate and an ac voltage source to excite it, put in series with the first one (or combine the two sources in one). You can still look at the input gate ac current by measuring the current through one of those voltage sources. Then make the ratio of the output drain current and that input gate current.
If you still insist on using a dc bias voltage source and an ac current source you should ac decouple the voltage source and the ac current source. For example put a big fat inductor in series with the dc voltage source but before the ac current source connects to the gate. This way for sufficiently high frequencies the ac current goes into the gate.
Anyway, I would prefer the setup with voltage sources only.
 

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    dfrndez

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spectre ft simulation

dfrndez said:
Thanks. The ac voltage approach is a bit unclear because I am looking for current gain.
Click to expand...
Hi dfrndez,

A term "current gain" has no practical meaning for a MOSFET since there is no base current which has a certain relationship to the drain current.
The only current through the base terminal is a parasitic one.
The only parameter which describes the input-output relationship is the transcnductance gm.

Added 20 min. later: The link to a CADENCE forum you have provided in your last post shows us that it is not advisable to believe everything we find in the net. (It is simply nonsens).
 

ft mos cgs spectre

what sutapanaki says is true. You can use AC and DC voltage sources and then (when plotting your response) use cadence calculator or the "Gain Magnitude" capability and select both the input and output leads where you what to measure the current ratio.

LvW, at very high frequencies the gate current of a MOSFET becomes slightly significant and you can actually measure a current-to-current gain. I still don't understand why dfrndez wants to do this, but theoretically you can.
 

simulating ft in spectre


Hi diemilio,

i consider it as very important for a technician/engineer to know the difference between
1.) parameters which determine the functional properties of a device leading to formulas which help designing a circuit, and
2.) parameters which are parasitic and do not influence other key parameters (like output current) in a foreseeable fashion.

Therefore, it does not matter if the gate current (which is a parasitic one) is significant or not - it has no direct influence on the output current (or even is the cause of the output current). And it really makes no sense to divide both currents with the aim to define something like a "current gain".
I doubt if you ever have seen any FET data sheet showing such a current gain ?
Is there any reason to define such a unrealistic term without any practical meaning ?
Regards
 

simulating ft

LvW, I couldn't agree more with you that a MOSFET is a voltage driven device, and that there's no sense of having a current to current gain, but that's only if you are considering an ideal transistor. For the purpose of this discussion we have to look at the big picture and take into account parasitics.
At low frequencies the capacitances Cgs (gate to source), Cgd (gate to drain), Cgb (gate to bulk) can be neglected so your MOSFET model is "ideal" in the sense that this capacitances are not included. If we calculate the current to current gain we will get ∞ value, since the input current is 0. In simulation CADENCE will show a HUGE number for converge purposes.
Now as frequency starts increasing Cgs, Cgd and Cgb come into play, so we will start seeing an effective impedance at the gate's input, so an AC current starts flowing into the MOSFET's gate (remember, not the ideal MOSFET but the realistic one that includes caps). This current is distributed between Cgd, Cgs and Cgb (so some of it flows into bulk, some of it int source and the rest goes to drain).
Since now we have a current flow, our current to current gain starts decreasing (because now we are dividing by a current value different than zero) until the point where Cgd is completely shorted (meaning that the input node is shorted with the output or drain node). When this happens you have reached ft, meaning that your device is completely useless because input and ouput are shorted.

Regards,

diemilio
 
mosfet ft cadence simulation


Diemilio, I know what you mean - however, I completely disagree.
At first, you cannot speak about "current gain" when there is no physical and causal relationship between both currents.
Secondly, in your "explanation" cited above you argue that the drain is "shorted" at a frequency which is equivalent to the frequency ft. This sounds, excuse me, a bit confusing and I cannot follow you.
At third - and that´s the main point: You have forgotten the main reason for the drain current decrease with frequency until ft is reached - the law of inertia which applies to the electrons resp. holes. Mainly this effect causes the current to decrease with frequency (as is the case for the BJT as well).

Added after 5 minutes:
LvW, I couldn't agree more with you that a MOSFET is a voltage driven device, and that there's no sense of having a current to current gain, but that's only if you are considering an ideal transistor. For the purpose of this discussion we have to look at the big picture and take into account parasitics.

Perhaps this sentence cited above makes clear what you mean:
At low frequencies the MOSFET is a voltage driven device - and suddenly at a certain frequency you think, that it becomes a current driven device with a "current gain". Sounds a bit uncommon, does it not ?
 

simulating ft of an nmos transistor

LvW,

There is a physical relation between input and output current; it's given by both the relation between parasitic capacitors (Cgd to Cgs+Cgb) and the transistor gain itself (which gives a certain drain current due to vgs at that point in frequency).

ft is the frequency at which your transistor isn't giving any gain (Frequency Transition - the frequency where gain falls to unity), meaning that your input and output signal are the same. I didn't forget about "law of inertia" but you have to remember that this effect is just part of the whole story. In BJTs this effect is usually modeled using tao-f and is typically embedded in the parasitic capacitor Cpi for practical purposes, but remember that there are other effects will cause your gain to drop (like for example the actual physical capacitors that form in between base and emitter, etc).

diemilio

Added after 10 minutes:


No, that's not what I mean. Sorry for not being clear enough. What I mean is that after a certain point you start getting a current "relation" between input and output.
 

mesfet cadence spectre

I think I will give it a go with both the ac voltage source and see what comes of that it is more intuitive and will probably lead to fewer issues with simulation. The reason I need to find ft is because the unity gain frequency can then be used to properly select a degeration inductance for the source of the LNA to properly match a real impedance. Also I believe the ratio between w/wt I believes dictates your NF for the LNA given power constraints. These parasitics are crucial in the design of LNA from an impedance matching perspective and from a performance, NF, perspective. I really appreciate the discussion.
 

ft mos simulation

OK diemilio, as I can do nothing else than to repeat my arguments: I give up .
Perhaps somebody else in the forum can contribute some new arguments to the discussion. Have a good time.
Regards
LvW

Just for clarification: With "law of inertia" I mean: mobility of the charge carriers (electrons resp. holes)
 

ac response in cadence

I side with LvW on this one. Yes, you can always form a ratio between the drain current and gate current as you can make a ratio between drain current and source current or drain current and bulk current. But this is not a current gain in the sense of what we have in bipolar transistors. For example if we increase the gate capacitance by layout or different shape of the geometry of the transistor then the Id/Ig will change but this is not something that fundamentally affects the operation of the MOS transistor.
 

spectre gate-drain cap

OK... I agree, this is going nowhere. Here you can find a couple of references to backup what I was trying to say.

Gray, Hurst, Lewis & Meyer - Analysis and Design Of Analog Integrated Circuits; 4th Edition; Chapter 1 (Section 1.6.8 ); Pages 55, 56, 57.

R. Jacob Baker - CMOS Circuit Design, Layout, and Simulation; 2nd Edition; Chapter 9 (Section 9.1.2); Pages 290, 291.

Behzad Razavi - Fundamentals of Microelectronics; Chapter 11 (Section 11.2.3); Pages 555, 556, 557.

Sedra & Smith - Microelectronic Circuits; 4th Edition; Part I; Chapter 5 (Section 5.10).

diemilio
 

gain frequency cadence

Yes, I agree that is how the Ft is defined - by measuring the Id/Ig which is called sometimes current gain. That is why I wrote in my previous post that this is not a current gain in the sense of what we have in bipolar transistors. MOST is a voltage controlled device. I think at least you can agree with that.
 

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