[SOLVED] FSM Verilog help with output

forast · Apr 16, 2014

ads-ee said:
According to a previous post you had to make assigns for all the state transitions. Did you do that translation? I've actually never had to do that before (I leave it to the synthesis tool, but I've checked the synth results). Just curious if you finished off the truth table I started or had another way of doing the translation from the case.

Regards

Not sure I did the truth table again before that post and I looked at it and is the same if not very close. I had to use the truth tables to do all the assigns and it all worked out. Before I didn't use the truth tables for the other assigns and next_states so it didn't work how it should've.

EDIT: Looked it over and yes same truth tables but my state transitions are different. Doesn't use A, B, C, etc.
Truthfully if I looked over this code it's very short and simple but a bit more difficult to understand than using states A, B, C, etc.

[SOLVED] FSM Verilog help with output

forast

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[SOLVED] FSM Verilog help with output

forast

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